HI5812 datasheet(4/13 Pages) INTERSIL

Part #	HI5812

Description	CMOS 20 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold

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Manufacturer	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

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4 / 13 page

6-1792

ANALOG INPUT

Input Current, Dynamic

At VIN = VREF+, 0V

-

±50

±100

-

±100

µA

Input Current, Static

Conversion Stopped

-

±0.4

±10

-

±10

µA

Input Bandwidth -3dB

-

1

-

MHz

Reference Input Current

-

160

-

µA

Input Series Resistance, RS

In Series with Input CSAMPLE

-

420

-

Ω

Input Capacitance, CSAMPLE

During Sample State

-

380

-

pF

Input Capacitance, CHOLD

During Hold State

-

20

-

pF

DIGITAL INPUTS OEL, OEM, STRT

High-Level Input Voltage, VIH

2.4

-

2.4

-

V

Low-Level Input Voltage, VIL

-

0.8

-

0.8

V

Input Leakage Current, IIL

Except CLK, VIN = 0V, 5V

-

±10

-

±10

µA

Input Capacitance, CIN

-10-

-

pF

DIGITAL OUTPUTS

High-Level Output Voltage, VOH

ISOURCE = -400µA

4.6

-

4.6

-

V

Low-Level Output Voltage, VOL

ISINK = 1.6mA

-

0.4

-

0.4

V

Three-State Leakage, IOZ

Except DRDY, VOUT = 0V, 5V

-

±10

-

±10

µA

Output Capacitance, COUT

Except DRDY

-

20

-

pF

CLOCK

High-Level Output Voltage, VOH

ISOURCE = -100µA (Note 2)

4

-

4

-

V

Low-Level Output Voltage, VOL

ISINK = 100µA (Note 2)

-

1

-

1

V

Input Current

CLK Only, VIN = 0V, 5V

-

±5-

±5mA

TIMING

Conversion Time (tCONV + tACQ)

(Includes Acquisition Time)

20

-

20

-

µs

Clock Frequency

Internal Clock, (CLK = Open)

200

300

400

150

500

kHz

External CLK (Note 2)

0.05

2

1.5

0.05

1.5

MHz

Clock Pulse Width, tLOW, tHIGH

External CLK (Note 2)

100

-

100

-

ns

Aperture Delay, tDAPR

(Note 2)

-

35

50

-

70

ns

Clock to Data Ready Delay, tD1DRDY

(Note 2)

-

105

150

-

180

ns

Clock to Data Ready Delay, tD2DRDY

(Note 2)

-

100

160

-

195

ns

Start Removal Time, tRSTRT

(Note 2)

75

30

-

75

-

ns

Start Setup Time, tSUSTRT

(Note 2)

85

60

-

100

-

ns

Start Pulse Width, tWSTRT

(Note 2)

10

4

-

15

-

ns

Start to Data Ready Delay, tD3 DRDY

(Note 2)

-

65

105

-

120

ns

Clock Delay from Start, tDSTRT

(Note 2)

-

60

-

ns

Output Enable Delay, tEN

(Note 2)

-

20

30

-

50

ns

Output Disabled Delay, tDIS

(Note 2)

-

80

95

-

120

ns

POWER SUPPLY CHARACTERISTICS

Supply Current, IDD + IAA

-

1.9

5

-

8

mA

NOTE:

2. Parameter guaranteed by design or characterization, not production tested.

Electrical Speciﬁcations

VDD = VAA+ = 5V, VREF+ = +4.608V, VSS = VAA- = VREF- = GND, CLK = External 750kHz,

Unless Otherwise Speciﬁed (Continued)

PARAMETER

TEST CONDITIONS

25oC

-40oC TO 85oC

UNITS

MIN

TYP

MAX

MIN

MAX

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