8

inputs are 50

Ω lines, then 50Ω termination resistors should

be placed as close to the converter inputs as possible

connected to the digital ground plane (if separate grounds

are used).

Ground Plane(s)

If separate digital and analog ground planes are used, then

all of the digital functions of the device and their

corresponding components should be over the digital ground

plane and terminated to the digital ground plane. The same

is true for the analog components and the analog ground

plane.

Noise Reduction

To minimize power supply noise, 0.1

µF capacitors should

be placed as close as possible to the converter’s power

designed using separate digital and analog ground planes,

these capacitors should be terminated to the digital ground

filtering of the power supplies on the board is

recommended.

Voltage Reference

The internal voltage reference of the device has a nominal

value of +1.2V with a

full temperature range of the converter. It is recommended

that a 0.1

µF capacitor be placed as close as possible to the

REFIO pin, connected to the analog ground. The REFLO

pin (16) selects the reference. The internal reference can

be selected if pin 16 is tied low (ground). If an external

reference is desired, then pin 16 should be tied high (to the

analog supply voltage) and the external reference driven

into REFIO, pin 17. The full scale output current of the

converter is a function of the voltage reference used and

range, through operation below 2mA is possible, with

performance degradation.

approximately 1.16V (pin 18). If an external reference is

If the full scale output current is set to 20mA by using the

internal voltage reference (1.16V) and a 1.86k

resistor, then the input coding to output current will resemble

the following:

Outputs

IOUTA and IOUTB are complementary current outputs. The

sum of the two currents is always equal to the full scale

output current minus one LSB. If single ended use is

desired, a load resistor can be used to convert the output

current to a voltage. It is recommended that the unused

output be either grounded or equally terminated. The voltage

developed at the output must not violate the output voltage

chosen so that the desired output voltage is produced in

conjunction with the output full scale current, which is

described above in the ‘Reference’ section. If a known line

impedance is to be driven, then the output load resistor

should be chosen to match this impedance. The output

voltage equation is:

These outputs can be used in a differential-to-single-ended

arrangement to achieve better harmonic rejection. The

SFDR measurements in this data sheet were performed with

a 1:1 transformer on the output of the DAC (see Figure 1).

With the center tap grounded, the output swing of pins 21

and 22 will be biased at zero volts. It is important to note

here that the negative voltage output compliance range limit

with this configuration. The loading as shown in Figure 1 will

result in a 500mV signal at the output of the transformer if

the full scale output current of the DAC is set to 20mA.

TABLE 1. INPUT CODING vs OUTPUT CURRENT

INPUT CODE (D7-D0)

IOUTA (mA)

IOUTB (mA)

111 11111

20

0

100 00000

10

10

000 00000

0

20

PIN 21

PIN 22

100

Ω

HI5660

50

Ω

50

Ω

50

Ω

IOUTB

IOUTA

FIGURE 4.

HI5660