4-1236

Typical Application Circuits

NOTE:

1. The clamp pulse is latched by the sampling clock of ADC, but that is not necessary for basic clamp operaiotn. However, slight small beat

may be generated as Vertical sag according to the relationship between the sampling frequency and the clamp pulse frequency. At such

time, the latch circuit is efective in this case.

FIGURE 1. WHEN CLAMP IS USED (SELF BIAS)

NOTES:

3.

FIGURE 2. DIGITAL CLAMP (SELF BIAS)

8

7

6

5

4

3

2

1

16

15

14

13

12

11

10

9

25

26

27

28

29

30

31

32

CLOCK IN

10

µ

0.1

µ

+3.3V (DIGITAL)

CLAMP PULSE IN

VIDEO IN

LATCH CK

Q

75

Ω

0.01

µ

10p

0.1

µ

GND (ANALOG)

GND (DIGITAL)

D0

D1

D2

D3

D4

D5

D6

D7

HC04

(NOTE 2)

0.01

µ

+3.3V (ANALOG)

+3.3V

(ANALOG)

0.01

µ

OPEN

20K

+

17

18

19

20

21

22

23

24

DAC,

PWM,

ETC.

CLAMP LEVEL

SETTING DATA

16

15

14

13

12

11

10

9

25

26

27

28

29

30

31

32

CLOCK IN

10

µ

0.1

µ

+3.3V (DIGITAL)

VIDEO IN

75

Ω

0.01

µ

10p

0.1

µ

GND (ANALOG)

GND (DIGITAL)

HC04

0.01

µ

+3.3V (ANALOG)

0.01

µ

OPEN

+

17

18

19

20

21

22

23

24

8

7

6

5

4

3

2

1

SUBTRACTER,

COMPARATOR,

ETC.

INFORMATION OTHER THAN

CLAMP INTERVAL IS AT

HIGH IMPEDANCE.

HI2300