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ADATE207 Datasheet(PDF) 1 Page - Analog Devices |
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ADATE207 Datasheet(HTML) 1 Page - Analog Devices |
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1 / 36 page  Quad Pin Timing Formatter ADATE207 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. FEATURES 4-channel timing formatter 256 waveforms per channel 4 independent event edges per waveform STIL IEEE 1450-1999-compatible events 4-period range for each edge 39.06 ps timing resolution 2.5 ns minimum edge refire rate All drive formats supported 100 MHz base vector rate ×2 and ×4 high speed modes ×2 pin multiplexing 1 ns minimum pulse width 32-bit fail counter per channel 4-bit pin capture per channel Air cooled, low power CMOS design 6 W at 100 MHz base rate 2.5 V power supply Differential DCL interface control TMU multiplexer APPLICATIONS Automatic test equipment (ATE) High speed digital instrumentation Pulse generation FUNCTIONAL BLOCK DIAGRAM TIME SET MEMORY FORMAT COMPARE LOGIC QUAD EDGE GENERATOR FAIL DETECTION PATTERN FAIL DCL INTERFACE TIME SET MEMORY FORMAT COMPARE LOGIC QUAD EDGE GENERATOR FAIL DETECTION PATTERN FAIL DCL INTERFACE TIME SET MEMORY FORMAT COMPARE LOGIC QUAD EDGE GENERATOR FAIL DETECTION PATTERN FAIL DCL INTERFACE TIME SET MEMORY FORMAT COMPARE LOGIC QUAD EDGE GENERATOR FAIL DETECTION PATTERN FAIL DCL INTERFACE ADATE207 Figure 1. GENERAL DESCRIPTION The ADATE207 is a timing generator and formatter for auto- matic test equipment (ATE) equipment. The ADATE207 provides four independent channels with a 100 MHz base vector rate of timing and formatting for ATE digital pins. It interfaces between the pattern memory,and the driver, comparator, and load (DCL) chips for complete digital pins. The ADATE207 accepts up to eight bits of pattern data per pin and can produce formatted outputs and perform comparisons of DUT expected responses. Each channel of the ADATE207 provides 256 selectable wave- forms, wherein each waveform consists of up to four possible events. Each event consists of a programmable timing edge and a STIL-compatible (IEEE Standard 1450-1999) set. Each timing edge generator can produce an edge with a span of four periods with a 39.06 ps edge placement resolution. The delay generators use a reference master clock of 100 MHz and provide programmable delays based upon counts of the clock and a compensated CMOS analog timing vernier. The programmable delay generators can be additionally delayed by a global 8-bit input value that is shared across all edges. The format and compare logic support ×2 pin multiplexing to allow the trading of pin count for speed. Each channel provides a 4-bit DUT output capture supporting mixed signal receive memory applications. The fail detection logic includes a 32-bit fail accumulation register per channel. An external TMU is supported with three 8-to-1 multiplexers. This allows the dual comparator outputs of any pin to be multiplexed to any of the three outputs: arm, start, or stop signals. |
Similar Part No. - ADATE207_15 |
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Similar Description - ADATE207_15 |
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