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ADADC85 Datasheet(PDF) 10 Page - Analog Devices |
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ADADC85 Datasheet(HTML) 10 Page - Analog Devices |
10 / 12 page AD ADC84/AD ADC85 Rev. B | Page 10 of 12 CLOCK RATE CONTROL ALTERNATE CONNECTIONS If adjustment of the CLOCK RATE is desired for faster conver- sion speeds, the CLOCK RATE CONTROL may be connected to an external multiturn trim potentiometer with a TCR of ±100 ppm/°C or less as shown in Figure 14 and Figure 15. If the potentiometer is connected to –15 V, conversion time can be increased as shown in Figure 5. If these adjustments are used, delete the connections shown in Table 2 for Pin 17. See Figure 2 for nonlinearity error versus conversion speed and Figure 5 for the effect of the control voltage on clock speed. Figure 14. 12-Bit Clock Rate Control Optional Fine Adjust Figure 15. 8-Bit Clock Rate Control Optional Fine Adjust MICROPROCESSOR INTERFACING The fast conversion times of the AD ADC84/AD ADC85 suggests several methods of interface to microprocessors. In systems where the ADC is used for high sampling rates on a single signal which is to be digitally processed, CPU-controlled conversion may be inefficient due to the slow cycle times of most microprocessors. It is generally preferable to perform conversions independently, inserting the resultant digital data directly into memory. This can be done using direct memory access (DMA), which is totally transparent to the CPU. Interface to user-designed DMA hardware is facilitated by the guaranteed data validity on the falling edge of the EOC signal. Clearly, 12 bits of data must be broken up for interface to a 8-bit wide data bus. There are two possible formats: right-justified and left-justified. In a right-justified system, the least significant 8 bits occupy one byte and the four MSBs reside in the low nibble of another byte. This format is useful when the data from the ADC is being treated as a binary number between 0 and 4095. The left-justified format supplies the eight most- significant bits in one byte and the 4 LSBs in the high nibble of another byte. The data now represents the fractional binary number relating the analog signal to the full-scale voltage. An advantage to this organization is that the most-significant eight bits can be read by the processor as a coarse indication of the true signal value. The full 12-bit word can then be read only when all 12 bits are needed. This allows faster and more efficient control of a process. Figure 16 shows a typical connection of 8085-type bus, using a left-justified data format for unipolar inputs. Status polling is optional, and can be read simultaneously with the 4LSBs. If it is desired to right-justify the data, pins 1 through 12 of the ADADC84/AD ADC85 should be reversed, as well as the connections to the data bus high and low byte address signals. When dealing with bipolar inputs (±5V, ±10V ranges), using the MSB directly yields a complementary offset binary-coded output. If complementary twos complement coding is desired, it can be produced be substituting MSB (Pin 13) for the MSB. This facilitates the arithmetic operation which are subsequently performed on the ADC output data. Figure 16. AD ADC84/AD ADC85 – 8085A Interface Connections |
Similar Part No. - ADADC85_15 |
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Similar Description - ADADC85_15 |
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