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HFA3860IV Datasheet(PDF) 6 Page - Intersil Corporation |
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HFA3860IV Datasheet(HTML) 6 Page - Intersil Corporation |
6 / 40 page 4- 6 NOTES: 1. The HFA3860 always uses the rising edge of SCLK. SD, R/W and CS hold times allow the controller to use either the rising or falling edge. 2. This port operates essentially the same as the HFA 3824 with the exception that the AS signal of the 3824 is not required. FIGURE 2. CONTROL PORT READ TIMING FIGURE 3. CONTROL PORT WRITE TIMING 7 6 5 4 32 10 7 6 5 4 32 10 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCLK SD CS R/W LSB DATA OUT MSB MSB ADDRESS IN FIRST ADDRESS BIT FIRST DATABIT OUT 7 6 5 4 321076543 210 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 SCLK SD CS R/W LSB DATA IN MSB MSB ADDRESS IN TABLE 1. CONFIGURATION AND CONTROL INTERNAL REGISTER LIST CONFIGURATION REGISTER NAME TYPE REGISTER ADDRESS HEX CR0 Part/Version Code R 00 CR1 I/O Polarity R/W 04 CR2 TX and RX Control R/W 08 CR3 A/D_CAL_POS Register R/W 0C CR4 A/D_CAL_NEG Register R/W 10 CR5 CCA Antenna Control R/W 14 CR6 Preamble Length R/W 18 CR7 Scramble_Tap (RX and TX) R/W 1C CR8 RX_SQ1_ ACQ (High) Threshold R/W 20 CR9 RX-SQ1_ ACQ (Low) Threshold R/W 24 CR10 RX_SQ2_ ACQ (High) Threshold R/W 28 CR11 RX-SQ2_ ACQ (Low) Threshold R/W 2C CR12 SQ1 CCA Thresh (High) R/W 30 CR13 SQ1 CCA Thresh (Low) R/W 34 CR14 ED or RSSI Thresh R/W 38 CR15 SFD Timer R/W 3C CR16 Signal Field (BPSK - 11 Chip Sequence) R/W 40 CR17 Signal Field (QPSK - 11 Chip Sequence) R/W 44 HFA3860 |
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Similar Description - HFA3860IV |
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