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HFA3841CN Datasheet(PDF) 8 Page - Intersil Corporation |
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HFA3841CN Datasheet(HTML) 8 Page - Intersil Corporation |
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8 / 27 page  8 SYNTHESIZER SPCLK Period tCYC 90 - 4,000 ns SPCLK Width Hi tH1 tCYC/2 - 10 - tCYC/2 + 10 ns SPCLK Width Lo tL1 tCYC/2 - 10 - tCYC/2 + 10 ns SYNCLE to Rising Edge SPCLK tD1 35 - - ns SPDATA Hold Time from Falling Edge of SPCLK tD2 0- - ns SPCLK Falling Edge to SYNLE Inactive tD3 35 - - ns SERIAL PORT - HFA3824A/HFA3860B SPCLK Clock Period tCYC 90ns - 4 µs High Period tH1, tL1 tCYC/2 -10 - tCYC/2 + 10 Delay from Clock Falling Edge to SPCSx, SPAS, SPREAD, SPDATA Outputs tCD -10- ns Setup Time of SPDATA Read to SPCLK Falling Edge tDRS 15 - - ns Hold Time of SPDATA Read from SPCLK Falling Edge tDRH 0- - Hold Time of SPDATA Write from SPCLK Falling Edge tDWH 0- - SYSTEM INTERFACE - PC CARD IO READ 16 Data Delay After SIORDN tDIORD - - 100 ns Data Hold Following SIORDN tHIORD 0- - ns SIORDN Width Time tWIORD 165 - - ns Address Setup Before SIORDN tSUA 70 - - ns SCE(1,2)N Setup Before SIORDN tSUCE 5- - ns SCE(1,2)N Hold After SIORDN tHCE 20 - - ns SREGN Setup Before SIORDN tSUREG 5- - ns SREGN Hold Following SIORDN tHREG 0- - ns SINPACKN Delay Falling from SIORDN tDFINPACK 0 - 45 ns SINPACKN Delay Rising from SIORDN dDRINPACK - - 45 ns SIOIS16N Delay Falling from Address tDFIOIS16 - - 35 ns SIOIS16N Delay Rising from Address tDRIOIS16 - - 35 ns SWAITN tDFWT - - 35 ns Data Delay from SWAITN Rising tDRWT -- 0 ns SWAITN Width Time tWWT - - 12,000 ns SYSTEM INTERFACE - PC CARD IO WRITE 16 Data Setup Before SIOWRN tSUIOWR 60 - - ns Data Hold Following SIOWRN tHIOWR 30 - - ns SIOWRN Width Time tWIOWR 165 - - ns Address Setup Before SIOWRN tSUA 70 - - ns Address Hold Following SIOWRN tHA 20 - - ns SCE(1,2)N Setup Before SIOWRN tSUCE 5- - ns SCE(1,2)N Hold Following SIOWRN tHCE 20 - - ns SREGN Setup Before SIOWRN tSUREG 5- - ns SREGN Hold Following SIOWRN tHREG 0- - ns AC Electrical Specifications (Continued) PARAMETER SYMBOL MIN TYP MAX UNITS Preliminary - HFA3841 |
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Similar Description - HFA3841CN |
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