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AD9870 Datasheet(PDF) 11 Page - Analog Devices |
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AD9870 Datasheet(HTML) 11 Page - Analog Devices |
11 / 20 page REV. 0 AD9870 –11– The recommended setting for LOFA is LOR/16. Choosing a larger value for LOFA will increase T. Thus, for a given phase difference between the LO input and the fREF input, the instan- taneous charge pump current will be less than that available for a LOFA value of LOR/16. Similarly, a smaller value for LOFA will decrease T, making more current available for the same phase difference. In other words, a smaller value of LOFA will enable the synthesizer to settle faster in response to a frequency hop than will a large LOFA value. Care must be taken to choose a value of LOFA which is large enough (values greater than four recommended) to prevent the loop from oscillating back and forth in response to a frequency hop. Table V. SPI Registers Associated with LO Synthesizer A ddress Bit (Hex) Breakdown Width Default Value Name 0x00 (7:0) 8 0xFF STBY 0x08 (5:0) 6 0x00 LOR(13:8) 0x09 (7:0) 8 0x38 LOR(7:0) 0x0A (7:5) 3 0x5 LOA (4:0) 5 0x00 LOB(12:8 0x0B (7:0) 8 0x1D LOB(7:0) 0x0C (6) 1 0 LOF (5) 1 0 LOINV (4:2) 3 0 LOI (1:0) 2 0 LOTM 0x0D (3:0) 4 0x0 LOFA(13:8) 0x0E (7:0) 8 0x04 LOFA(7:0) CLOCK SYNTHESIZER The clock synthesizer is a fully programmable integer-N PLL capable of 2.2 kHz resolution at clock input frequencies up to 18 MHz and reference frequencies up to 25 MHz. It is similar to the LO synthesizer described previously in Figure 4 with the following exceptions: • It does not include an 8/9 prescaler nor an A Counter. • It includes a negative-resistance core which when used in conjunction with an external varactor serves as the VCO. The 14-bit reference counter and 13-bit N-divider counter can be programmed via the following registers: CKR and CKN. The charge pump current is programmable via the CKI register from 0.625 mA to 5.0 mA using the following equation: IPUMP = (CKI + 1) × 0.625 mA. The fast acquire subcircuit of the charge pump is controlled by the CKFA register in the same manner as the LO synthesizer is controlled by the LOFA register. An on-chip lock detect func- tion (enabled by the CKF bit) automatically increases the output current for faster settling during channel changes. The synthe- sizer may also be disabled using the CKOB standby bit located in the STBY register. 2 CLK OSC. BIAS IBIAS = 0.25, 0.35, 0.53, OR 0.85 mA VDDC=3.0 V IOUTC LOSC 0.1 F RBIAS COSC LOOP FILTER CVAR RD AD9870 CLKN CLKP VCM = VDDC – RBIAS IBIAS > 1.6V f OSC > (2 LOSC (CVARACTOR//COSC))–1/2 Figure 6. External Loop Filter, Varactor and L-C Tank Are Required to Realize a Complete Clock Synthesizer The AD9870 clock synthesizer circuitry includes a negative- resistance core so that only an external L-C tank circuit with a varactor is needed to realize a voltage controlled oscillator (VCO). Figure 6 shows the external components required to complete the clock synthesizer along with the equivalent input of the CLK input. The resonant frequency of the VCO is approximately deter- mined by LOSC and the series equivalent capacitance of COSC and CVAR. As a result, LOSC, COSC, and CVAR should be selected to provide sufficient tuning range to ensure proper locking of the clock synthesizer The bias, IBIAS, of the negative-resistance core has four programmable settings. Lower equivalent Q of the L-C tank circuit may require a higher bias setting of the negative- resistance core to ensure proper oscillation. RBIAS should be selected such that the common-mode voltage at CLKP and CLKN is approximately 1.6 V. The synthesizer may be disabled via the CK standby bit to allow the user to employ an external synthesizer and/or VCO in place of those resident on the IC. Table VI. SPI Registers Associated with CLK Synthesizer A ddress Bit (Hex) Breakdown Width Default Value Name 0x00 (7:0) 8 0xFF STBY 0x01 (3:2) 2 0 CKOB 0x10 (5:0) 6 00 CKR(13:8) 0x11 (7:0) 8 0x38 CKR(7:0) 0x12 (4:0) 5 0x00 CKN(12:8) 0x13 (7:0) 8 0x3C CKN(7:0) 0x14 (6) 1 0 CKF (5) 1 0 CKINV (4:2) 3 0 CKI (1:0) 1 0 CKTM 0x15 (3:0) 4 0x0 CKFA(13:8) 0x16 (7:0) 8 0x04 CKFA(7:0) |
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