AD9834_15 datasheet(6/32 Pages) AD

Part #	AD9834

Description	20 mW Power, 2.3 V to 5.5 V

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Manufacturer	AD [Analog Devices]

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AD9834

Data Sheet

TIMING CHARACTERISTICS

DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.

Table 2.

Parameter1

Limit at TMIN to TMAX

Unit

Test Conditions/Comments

t1

20/13.33

ns min

MCLK period: 50 MHz/75 MHz

t2

8/6

ns min

MCLK high duration: 50 MHz/75 MHz

t3

8/6

ns min

MCLK low duration: 50 MHz/75 MHz

t4

25

ns min

SCLK period

t5

10

ns min

SCLK high duration

t6

10

ns min

SCLK low duration

t7

5

ns min

FSYNC-to-SCLK falling edge setup time

t8 MIN

10

ns min

FSYNC-to-SCLK hold time

t8 MAX

t4 − 5

ns max

t9

5

ns min

Data setup time

t10

3

ns min

Data hold time

t11

8

ns min

FSELECT, PSELECT setup time before MCLK rising edge

t11A

8

ns min

FSELECT, PSELECT setup time after MCLK rising edge

t12

5

ns min

SCLK high to FSYNC falling edge setup time

1

Guaranteed by design, not production tested.

Timing Diagrams

MCLK

t1

t3

t2

Figure 3. Master Clock

FSELECT,

PSELECT

VALID DATA

MCLK

t11A

t11

Figure 4. Control Timing

D0

SCLK

FSYNC

SDATA

D15

D14

D2

D1

D15

D14

t12

t7

t6

t8

t5

t4

t9

t10

Figure 5. Serial Timing

Rev. D | Page 6 of 32

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