2

Functional Diagram

TRUTH TABLE

OPERATING MODE

INPUTS

OUTPUTS

MR

CP

PE

TE

SPE

Pn

Qn

TC

Reset (Clear)

L

X

X

X

X

X

L

L

Parallel Load

H

X

X

l

l

L

L

H

X

X

l

h

H

(Note 1)

Count

H

h

h

h (Note 3)

X

Count

(Note 1)

Inhibit

H

X

l (Note 2)

X

h (Note 3)

X

qn

(Note 1)

H

X

X

l (Note 2)

h (Note 3)

X

qn

L

H = HIGH voltage level.

L = LOW voltage level.

h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition.

l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition.

X = Immaterial.

q = Lower case letter indicate the state of the referenced output prior to the LOW-to-HIGH clock transition.

= LOW-to-HIGH clock transition.

NOTES:

1. The TC output is HIGH when TE is HIGH and the counter is at terminal count (HHHH for 161 and HLLH for 160).

2. The HIGH-to-LOW transition of PE or TE on the 54/74161 and 54/74160 should only occur while CP is high for conventional operation.

3. The LOW-to-HIGH transition of SPE on the 54/74161 and 54/74160 should only occur while CP is high for conventional operation.

SPE

MR

CP

PE

TE

MR

D0

T0

CP

P

Q0

Q0

Q0

14

15

TC

MR

D1

T1

CP

P

Q1

Q1

13

MR

D2

T2

CP

P

Q2

Q0

12

MR

D3

T3

CP

P

Q3

Q1

11

Q0

Q3 Q3

Q3 Q0 Q3 Q0

Q0 Q1

Q2 Q3

Q0 Q3

Q0

Q1

Q2

P3

P2

P1

P0

34

56

GND

16

8

HCTS160T