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AD9518-0 Datasheet(PDF) 10 Page - Analog Devices |
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AD9518-0 Datasheet(HTML) 10 Page - Analog Devices |
10 / 64 page AD9518-0 Data Sheet Rev. C | Page 10 of 64 SERIAL CONTROL PORT Table 13. Parameter Min Typ Max Unit Test Conditions/Comments CS (INPUT) CS has an internal 30 kΩ pull-up resistor Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 3 µA Input Logic 0 Current 110 µA Input Capacitance 2 pF SCLK (INPUT) SCLK has an internal 30 kΩ pull-down resistor Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 110 µA Input Logic 0 Current 1 µA Input Capacitance 2 pF SDIO (WHEN INPUT) Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 10 nA Input Logic 0 Current 20 nA Input Capacitance 2 pF SDIO, SDO (OUTPUTS) Output Logic 1 Voltage 2.7 V Output Logic 0 Voltage 0.4 V TIMING Clock Rate (SCLK, 1/tSCLK) 25 MHz Pulse Width High, tHIGH 16 ns Pulse Width Low, tLOW 16 ns SDIO to SCLK Setup, tDS 2 ns SCLK to SDIO Hold, tDH 1.1 ns SCLK to Valid SDIO and SDO, tDV 8 ns CS to SCLK Setup and Hold, tS, tH 2 ns CS Minimum Pulse Width High, tPWH 3 ns PD, SYNC, AND RESET PINS Table 14. Parameter Min Typ Max Unit Test Conditions/Comments INPUT CHARACTERISTICS These pins each have a 30 kΩ internal pull-up resistor Logic 1 Voltage 2.0 V Logic 0 Voltage 0.8 V Logic 1 Current 1 µA Logic 0 Current 110 µA Capacitance 2 pF RESET TIMING Pulse Width Low 50 ns SYNC TIMING Pulse Width Low 1.5 High speed clock cycles High speed clock is CLK input signal |
Similar Part No. - AD9518-0_15 |
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Similar Description - AD9518-0_15 |
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