7-135

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

HCS11MS

Radiation Hardened

Triple 3-Input AND Gate

Pinouts

14 PIN CERAMIC DUAL-IN-LINE

MIL-STD-1835 DESIGNATOR CDIP2-T14, LEAD FINISH C

TOP VIEW

14 PIN CERAMIC FLAT PACK

MIL-STD-1835 DESIGNATOR CDFP3-F14, LEAD FINISH C

TOP VIEW

A1

B1

A2

B2

C2

Y2

GND

VCC

C1

Y1

C3

B3

A3

Y3

1

2

3

4

5

6

7

14

13

12

11

10

9

8

14

13

12

11

10

9

8

2

3

4

5

6

7

1

A1

B1

A2

B2

C2

Y2

GND

VCC

C1

Y1

C3

B3

A3

Y3

Features

• 3 Micron Radiation Hardened SOS CMOS

• Total Dose 200K or 1 Mega-RAD(Si)

(Typ)

• Latch-Up Free Under Any Conditions

• Significant Power Reduction Compared to LSTTL ICs

• DC Operating Voltage Range: 4.5V to 5.5V

• Input Logic Levels

- VIL = 30% of VCC Max

- VIH = 70% of VCC Min

• Input Current Levels Ii

≤ 5µA at VOL, VOH

Description

The Intersil HCS11MS is a Radiation Hardened Triple 3-

Input AND Gate. A high on all inputs forces the output to a

High state.

The HCS11MS utilizes advanced CMOS/SOS technology to

achieve high-speed operation. This device is a member of

radiation hardened, high-speed, CMOS/SOS Logic Family.

The HCS11MS is supplied in a 14 lead Weld Seal Ceramic

flatpack (K suffix) or a Weld Seal Ceramic Dual-In-Line

Package (D suffix).

File Number

3048

November 1994

Truth Table

INPUTS

OUTPUTS

An

Bn

Cn

Yn

LLL

L

LL

H

L

LHL

L

LH

H

L

HL

L

L

HLH

L

HH

L

L

HHH

H

NOTE: L = Logic Level Low, H = Logic level High

Functional Diagram

An

Bn

Yn

Cn

(1, 3, 9)

(2, 4, 10)

(13, 5, 11)

(12, 6, 8)