AD8383_15 datasheet(7/16 Pages) AD

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AD8383

Rev. 0 | Page 7 of 16

TIMING DIAGRAMS

CLK

DB(0:9)

STSQ

XFR

VTH = 1.65V

tCLK LOW

tCLK HIGH

tHOLD

tSKEW

tSETUP

tHOLD

Figure 3. Timing Diagram, Even Mode (E/O = HIGH)

CLK

DB(0:9)

STSQ

XFR

VTH = 1.65V

tCLK LOW

tCLK HIGH

tHOLD

tSETUP

tSKEW

tHOLD

tSETUP

Figure 4. Timing Diagram, Odd Mode (E/O = LOW)

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