DG527BY datasheet(8/16 Pages) INTERSIL

Part #	DG527BY

Description	Analog CMOS Latchable Multiplexers

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Manufacturer	INTERSIL [Intersil Corporation]

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12-8

Minimum Input Timing Requirements Over Full Temperature Range

PARAMETER

MEASURED TERMINAL

MIN

UNITS

WRITE Pulse Width, tWW

WR, See Figure 1

300

ns

A, EN Data Valid After WRITE (Stabilization Time), tDW A0, A1, (A2), EN, WR; See Figure 1

180

ns

A, EN Data Valid After WRITE (Hold Time), tWD

A0, A1, (A2), EN, WR; See Figure 1

30

ns

RESET Pulse Width, tRS

RS, (Note 6), VS = 5V, See Figure 2

500

ns

NOTES:

1. Signals on VS, VD or VIN exceeding V+ or V- will be clamped by internal diodes. Limit diode forward current to maximum current ratings.

2. Typical values are for design aid only, not guaranteed and not subject to production testing.

3. The algebraic convention whereby the most negative value is a minimum, and most positive value is a maximum, is used in this datasheet.

4.

, where VS = input to OFF switch, and VD = output due to VS.

5. ID(ON) is leakage from driver into “ON” switch.

6. Period of Reset (RS) pulse must be at least 50

µs during or after power ON.

7. Parameter not tested. Parameter guaranteed by design or characterization.

Test Circuits and Waveforms

FIGURE 1. WR TIMING WAVEFORMS

FIGURE 2. RS TIMING WAVEFORMS

FIGURE 3A. tTRANSITION SWITCHING TIME TEST CIRCUIT

† Similar connections for DG526

FIGURE 3B. tTRANSITION SWITCHING TIME TEST CIRCUIT

† Similar connections for DG527

OFF Isolation

20

V

S

V

D

----------

=

3V

0

WR

A0, A1, (A2)

3V

0

1.5V

tWW

tDW

tWD

2.0V

0.8V

EN

3V

0

RS

VO

0V

SWITCH

OUTPUT

1.5V

tRS

tOFF(RS)

0.8VO

EN

RS

A0

S2 THRU S7

A1

A2

LOGIC

INPUT

50

Ω

+2.4V

SWITCH

OUTPUT

35pF

1M

Ω

+15V

-15V

+10V

±10V

GND

WR

V-

DG528

†

S1

S8

D

V+

VD

EN

RS

S2A THRU S4A ,

A0

A1

LOGIC

INPUT

50

Ω

+2.4V

SWITCH

OUTPUT

35pF

1M

Ω

+15V

-15V

+10V

±10V

GND

WR

V-

DG529

†

S1B

S4B

DB

V+

DA

S2B, AND S3B

VDB

DG526, DG527, DG528, DG529

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