4-129

CDP1883,

CDP1883C

CMOS 7-Bit Latch

and Decoder Memory Interfaces

March 1997

Features

• Performs Memory Address Latch and Decoder Func-

tions Multiplexed or Non-Multiplexed

• Interfaces Directly with the CDP1800-Series Micropro-

cessors

• Allows Decoding for Systems Up to 32K Bytes

Description

The CDP1883 is a CMOS 7-bit memory latch and decoder

circuit intended for use in CDP1800-series microprocessor

systems. It can serve as a direct interface between the multi-

plexed address bus of this system and up to four 8K x 8-bit

memories to implement a 32K-byte memory system. With

four 4K x 8-bit memories, a 16K-byte system can be

decoded.

The device is also compatible with non-multiplexed address

the latches are in the data-following mode and the decoded

outputs can be used in general-purpose memory-system

applications.

The CDP1833 is compatible with CDP1800-series micropro-

cessors operating at maximum clock frequency.

The CDP1883 and CDP1883C are functionally identical.

They differ in that the CDP1883 has a recommended operat-

ing voltage range of 4V to 10.5V and the C version has a

recommended operating voltage range of 4V to 6.5V.

The CDP1883 and CDP1883C are supplied in 20 lead dual-

in-line plastic packages (E Suffix).

Pinout

CDP1883, CDP1883C

(PDIP)

TOP VIEW

Ordering Information

5V

10V

TEMP.

RANGE

PACKAGE

PKG.

NO.

CDP1883CE CDP1883E

PDIP

E20.3

11

12

13

14

15

16

17

18

20

19

10

9

8

7

6

5

4

3

2

1

CLOCK

MA0

MA1

MA2

MA3

MA4

MA6

MA5

CE

A9

A10

A11

A8

A12

CS0

CS1

CS2

CS3

File Number

1507.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207