6-51

1800 CLOCK

A5

TPA

MRD

CEO

BUS

RAM CYCLE

CS1 = 1, CS2 = 0

(RAM SELECTED)

ROM CYCLE

(RAM DESELECTED)

VALID DATA

VALID DATA

OPERATING MODES

FUNCTION

MRD

MWR

CS1

• CS2

TPA

(NOTE 1)

CS/A5

CEO

CDP1800 Mode

Write

X

O

I

I

I

Read

O

I

I

I

I

Deselect

I

I

I

I

I

Deselect

I

X

O

X

X

I

Deselect

O

X

O

X

X

O

Deselect

I

X

X

O

I

Deselect

O

X

X

O

O

Non-CDP1800 Mode

Write

X

O

I

I

X

I

Read

O

I

I

I

X

I

Deselect

I

I

I

I

X

I

Deselect

I

X

O

I

X

I

Deselect

O

X

O

I

X

O

NOTE:

1. For CDP1800 Mode, refers to high order memory address bit level at time when TPA

transition takes

place.

FIGURE 3. CHIP ENABLE OUTPUT TIMING WAVEFORMS FOR CDP1800 BASED SYSTEMS

CDP1826C