6-21

PARAMETER

SYMBOL

(V)

LIMITS

UNITS

MIN

MAX

MIN

MAX

Read Cycle (Note 1)

5

370

-

500

-

ns

Access from Address (Note 1)

5

-

370

-

500

ns

Output Valid from Chip Select 1 (Note 1)

5

-

370

-

500

ns

Output Valid from Chip Select 2 (Note 1)

5

-

370

-

500

ns

Output Active from Output Disable (Note 1)

5

-

170

-

225

ns

Output Hold from Chip Select 1

5

10

-

20

-

ns

Output Hold from Chip Select 2

5

10

-

20

-

ns

Output Hold from Output Disable

5

10

-

20

-

ns

NOTE:

1. Limits designate 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing

NOTE: Minimum timing for valid data output. Longer times will initiate an

earlier but invalid output.

FIGURE 1. READ CYCLE WAVEFORMS AND TIMING DIAGRAM

FIGURE 2. MEMORY CELL CONFIGURATION

A0 - A7

CHIP

CHIP

OUTPUT

DISABLE

READ/

DATA OUT

SELECT 2

SELECT 1

WRITE

DATA OUT

VALID

HIGH

IMPEDANCE

HIGH

IMPEDANCE

(NOTE 1)

(NOTE 1)

(NOTE 1)

WRITE

ADDRESS

DECODER

READ

ADDRESS

DECODER

CDP1822C/3