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CD4516BMS Datasheet(PDF) 1 Page - Intersil Corporation |
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CD4516BMS Datasheet(HTML) 1 Page - Intersil Corporation |
1 / 11 page 1 CD4510BMS, CD4516BMS CMOS Presettable Up/Down Counters CD4510BMS Presettable BCD Up/Down Counter and the CD4516BMS Presettable Binary Up/Down counter consist of four synchronously clocked D-type flip-flops (with a gating structure to provide T-type flip-flop capability) connected as counters. These counters can be cleared by a high level on the RESET line, and can be preset to any binary number present on the jam inputs by a high level on the PRESET ENABLE line. The CD4510BMS will count out of non-BCD counter states in a maximum of two clock pulses in the up mode, and a maximum of four clock pulses in the down mode. If the CARRY IN input is held low, the counter advances up or down on each positive-going clock transition. Synchronous cascading is accomplished by connecting all clock inputs in parallel and connecting the CARRY OUT of a less significant stage to the CARRY IN of a more significant stage. The CD4510BMS and CD4516BMS can be cascaded in the ripple mode by connecting the CARRY OUT to the clock of the next stage. If the UP/DOWN input changes during a ter- minal count, the CARRY OUT must be gated with the clock, and the UP/DOWN input must change while the clock is high. This method provides a clean clock signal to the sub- sequent counting stage. (See Figures 13, 14.) These devices are similar to types MC14510 and MC14516. The CD4510BMS and CD4516BMS are supplied in these 16-lead outline packages: Features • High Voltage Types (20V Rating) • CD4510BMS - BCD Type • CD4516BMS - Binary Type • Medium Speed Operation - fCL = 8MHz Typ. at 10V • Synchronous Internal Carry Propagation • Reset and Preset Capability • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Standardized Symmetrical Output Characteristics • Maximum Input Current of 1 µA at 18V Over Full Pack- age Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Applications • Up/Down Difference Counting • Multistage Synchronous Counting • Multistage Ripple Counting • Synchronous Frequency Dividers Pinout CD4510BMS, CD4516BMS TOP VIEW Functional Diagram Braze Seal DIP *H4W †H45 Frit Seal DIP *FBF †H1F Ceramic Flatpack H6W *CD4510B Only †CD4516B Only 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 PRESET ENABLE Q4 P4 P1 CARRY IN Q1 VSS CARRY OUT VDD Q3 P3 P2 Q2 UP/DOWN RESET CLOCK Q1 Q2 Q3 Q4 6 11 14 2 P1 P2 P3 P4 4 12 13 3 CARRY OUT 7 CARRY IN 5 RESET CLOCK UP/DOWN 10 15 PRESET ENABLE VDD = 16 VSS = 8 1 9 Data Sheet December 1992 File Number 3338 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 |
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