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FTLX3912M336 Datasheet(PDF) 9 Page - Finisar Corporation. |
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FTLX3912M336 Datasheet(HTML) 9 Page - Finisar Corporation. |
9 / 14 page FTLX3912M3xx High Link Budget, DWDM XFP – Product Specification F i n i s a r Finisar Corporation September 18, 2013 Rev C4 Page 9 VIII. Digital Diagnostics Functions As defined by the XFP MSA 1, Finisar XFP transceivers provide digital diagnostic functions via a 2-wire serial interface, which allows real-time access to the following operating parameters: Transceiver temperature Laser bias current Transmitted optical power Received optical power Transceiver supply voltage It also provides a sophisticated system of alarm and warning flags, which may be used to alert end-users when particular operating parameters are outside of a factory-set normal range. The operating and diagnostics information is monitored and reported by a Digital Diagnostics Transceiver Controller (DDTC) inside the transceiver, which is accessed through the 2-wire serial interface. When the serial protocol is activated, the serial clock signal (SCL pin) is generated by the host. The positive edge clocks data into the XFP transceiver into those segments of its memory map that are not write-protected. The negative edge clocks data from the XFP transceiver. The serial data signal (SDA pin) is bi-directional for serial data transfer. The host uses SDA in conjunction with SCL to mark the start and end of serial protocol activation. The memories are organized as a series of 8-bit data words that can be addressed individually or sequentially. The 2-wire serial interface provides sequential or random access to the 8 bit parameters, addressed from 000h to the maximum address of the memory. For more detailed information, including memory map definitions, please see the XFP MSA documentation 1. 8.5Gb/s Fibre-Channel: To operate the FTLX3912M3xx at 8.5Gb/s Fibre-Channel, the EEPROM-Table 0, Byte 117, Bit 0 must be set as follows; . EEPROM Byte 117, Bit 0, value “1” for 8GFC: EEPROM Byte 117, Bit 0 value “0” for 10Gb/s rates: o (It is also possible to bypass the CDRs with, Byte 111, Bit 0.) By default, a power cycling the transceiver will return the transceiver to normal 10Gb/s operation with the CDRs active. |
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