7-825

CD4031BMS

FIGURE 11. CASCADING USING DELAYED CLOCKING FOR REDUCED CLOCK DRIVE REQUIREMENTS

FIGURE 12. CASCADING USING HALF-CLOCK-PULSE DELAYED OUTPUT (Q’) TO PERMIT

USE OF SLOW RISE AND FALL CLOCK INPUTS

Chip Dimensions and Pad Layout

15

10

1

6

9

CD4031BMS

RECIRC

IN

DATA

MODE

CONTROL

CLD

15

10

1

6

9

CD4031BMS

CLD

QD

15

10

1

6

9

CD4031BMS

CLD

D

Q

15

10

1

6

9

CD4031BMS

CLD

D

Q

Q

MODE CONTROL VDD = RECIRCULATION

GND = NEW DATA

VDD

22

2

2

CL

CL

CL

CL

CLOCK

DRIVER

D

CL

Q

FF

*

DELAYED

CLOCK

TO CLOCK

NEW DATA

INTO FIRST

REGISTER

(1/2 - CD4013B)

FF TO DELAY DATA UNTIL

FISRT REGISTERED DELAYED CLOCKING

HAS OCCURED

15

10

1

5

2

CD4031BMS

RECIRC

IN

DATA

MODE

CONTROL

CL

CLOCK DRIVER

15

10

1

5

2

CD4031BMS

CL

Q’

D

15

10

1

5

2

CD4031BMS

CL

D

Q’

15

10

1

5

2

CD4031BMS

CL

D

Q’

Q’

MODE CONTROL VDD = RECIRCULATION

GND = NEW DATA

VDD

6

Dimensions in parentheses are in millimeters

and are derived from the basic inch dimensions

METALLIZATION:

Thickness: 11k

Å

PASSIVATION:

10.4kÅ - 15.6k

BOND PADS:

0.004 inches X 0.004 inches MIN

DIE THICKNESS:

0.0198 inches - 0.0218 inches