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CD4031BMS Datasheet(PDF) 7 Page - Intersil Corporation |
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CD4031BMS Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 10 page 822 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com CD4031BMS Logic Diagram 15 DATA 1 IN * 10 MODE CONTROL * p n CL CL 1 * p n CL CL p n CL CL p n CL CL p n CL CL p n CL CL p n CL CL p n CL CL p n CL CL p n CL CL 5 7 6 Q’ QQ RECIRCULATE (DATA 2 IN) 63 IDENTICAL STAGES 9 2 * CLOCK CL CLD CL VDD VSS *ALL INPUTS ARE PROTECTED BY CMOS/MOS PROTECTION NETWORK INPUT CONTROL CIRCUIT TRUTH TABLE DATA RECIR MODE BIT INTO STAGE 1 1X0 1 0X0 0 X1 1 1 X0 1 0 1 = High Level X = Don’t Care 0 = Low Level NC = No Change TYPICAL STAGE TRUTH TABLE DATA CL DATA + 1 00 11 XNC 1 = High Level 0 = Low Level X = Don’t Care NC = No Change TRUTH TABLE FOR OUTPUT FROM Q’ (TERMINAL 5) DATA + 64 CL DATA + 64 1/2 00 11 XNC 1 = High Level 0 = Low Level X = Don’t Care NC = No Change |
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