7-359

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

CD4020BMS, CD4024BMS,

CD4040BMS

CMOS Ripple-Carry Binary

Counter/Dividers

Features

• High Voltage Types (20V Rating)

• Medium Speed Operation

• Fully Static Operation

• Buffered Inputs and Outputs

• 100% Tested for Quiescent Current at 20V

• Standardized Symmetrical Output Characteristics

• Common Reset

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current of 1

µa at 18V Over Full Pack-

age-Temperature Range;

• Noise Margin (Over Full Package Temperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Specifications For Description Of

‘B’ Series CMOS Devices”

Applications

• Control Counters

• Timers

• Frequency Dividers

• Time-Delay Circuits

Description

CD4020BMS, CD4024BMS, and CD4040BMS are ripple-

carry binary counters. All counter stages are master-slave

flip-flops. The state of a counter advances one count on the

negative transition of each input pulse; a high level on the

RESET line resets the counter to its all zeros state. Schmitt

trigger action on the input-pulse line permits unlimited rise

and fall times. All inputs and outputs are buffered.

The CD4020BMS, CD4024BMS and the CD4040BMS is

supplied in these 14 lead outline packages:

Pinouts

CD4020BMS

TOP VIEW

CD4024BMS

TOP VIEW

CD4040BMS

TOP VIEW

CD4020BMS - 14 Stage

CD4024BMS - 7 Stage

CD4040BMS - 12 Stage

CD4020B

CD4024B

CD4040B

Braze Seal DIP

H4W

H4Q

H4X

Frit Seal DIP

H1F

H1B

H1F

Ceramic Flatpack

H6W

H3W

H6W

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

Q12

Q13

Q14

Q6

Q5

Q7

VSS

Q4

VDD

Q10

Q8

Q9

RESET

θ

Q1

Q11

θ

RESET

Q7

Q6

Q5

Q4

VSS

VDD

NC

Q1

Q2

NC

Q3

NC

1

2

3

4

5

6

7

14

13

12

11

10

9

8

NC = NO CONNECTION

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

Q12

Q6

Q5

Q7

Q4

Q3

VSS

Q2

VDD

Q10

Q8

Q9

R

θ

Q1

Q11

File Number

3300.1

October 1996