7-1431

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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CD40208BMS

CMOS 4 x 4 Multiport Register

Description

The CD40208BMS is a 4 x 4 multiport register containing

four 4-bit registers, write address decoder, two separate

read address decoders, and two 3-state output buses.

When the ENABLE input is low, the corresponding output

bus is switched, independently of the clock, to a high imped-

ance state. The high impedance third state provides the out-

puts with the capability of being connected to the bus lines in

a bus organized system without the need for interface or

pull-up components.

When the WRITE ENABLE input is high, all data input lines

are latched on the positive transition of the CLOCK and the

data is entered into the word selected by the write address

lines. When WRITE ENABLE is low, the CLOCK is inhibited

and no new data is entered. In either case, the contents of

any word may be accessed via the read address lines inde-

pendent of the state of the CLOCK input.

The CD40208BMS types are supplied in hermetic 24-lead

dual-in-line ceramic packages (D and F suffixes), 24-lead

dual-in-line plastic packages (E suffix), 24-lead ceramic flat

packages (K suffix), and in chip form (H suffix).

The CD40208BMS is supplied in these 24-lead outline pack-

ages:

Braze Seal DIP

HNZ

Ceramic Flatpack

H4P

Features

• High Voltage Types (20V Rating)

• One Input and Two Output Buses

• Unlimited Expansion in Bit and Word Directions

• Data Lines have Latched Inputs

• 3-State Outputs

• Separate Control of Each Bus, Allowing Simultaneous

Independent Reading of any of Four Registers on Bus

A and Bus B and Independent Writing Into any of the

Four Registers

• 100% Tested for Quiescent Current at 20V

• Standardized, Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current of 1

µA at 18V Over Full Pack-

• Noise Margin (Full Package-Temperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Stan-

dards No. 13B, “Standard Specifications for Descrip-

tion of “B” Series CMOS Devices”

Applications

• Scratch Pad Memories

• Arithmetic Units

• Data Storage

December 1992

File Number

3396

Pinout

CD40208BMS

TOP VIEW

1

2

3

4

5

6

7

8

9

10

11

12

Q3B

Q2B

ENABLE A

Q0A

Q1A

Q2A

Q3A

WRITE 0

WRITE 1

READ 0B

READ 1B

VSS

16

17

18

19

20

21

22

23

24

15

14

13

VDD

Q0B

ENABLE B

D0

D1

D3

WRITE ENABLE

READ 1A

READ 0A

Q1B

D2

CLOCK

Functional Diagram

WRITE

ENABLE

ENABLE A

3

15

20

19

18

17

8

9

14

13

11

10

4

5

6

7

22

23

2

1

Q0

Q1

Q2

Q3

Q0

Q1

Q2

Q3

READ 1A

READ 0A

READ 1B

READ 0B

16

21

WRITE 1

WRITE 0

D0

D1

D2

D3

DATA

INPUTS

WORD A

OUTPUT

WORD B

OUTPUT

CLOCK

ENABLE B