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CD40107 Datasheet(PDF) 6 Page - Intersil Corporation |
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CD40107 Datasheet(HTML) 6 Page - Intersil Corporation |
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6 / 7 page  7-23 CD40107BMS Schematic FIGURE 1. 1 OF 2 GATES Typical Performance Characteristics FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 4. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE FIGURE 5. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE VDD A * 3, (11) VSS B * 4, (10) C = A • B 5, (9) VDD = 14 VSS = 7 NOTE: 1 OF 2 GATES (NUMBERS IN PARENTHESES ARE TERMINAL NUMBERS FOR SECOND GATE) VDD VSS * ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK TRUTH TABLE AB C 0 0 1* Z** 1 0 1* Z** 0 1 1* Z** 110 * Requires external pull-up resistor (RL) to VDD. ** Without pull-up resistor (3-state). 10V 5V AMBIENT TEMPERATURE (TA) = +25 oC GATE-TO-SOURCE VOLTAGE (VGS) = 15V 0 5 10 15 480 320 160 640 800 960 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 10V 5V AMBIENT TEMPERATURE (TA) = +25 oC GATE-TO-SOURCE VOLTAGE (VGS) = 15V 0 5 10 15 240 160 80 320 400 480 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) AMBIENT TEMPERATURE (TA) = +25 oC RL = 120 Ω TO VDD SUPPLY VOLTAGE (VDD) = 5V tTLH 5V tTHL 10V tTLH 15V tTLH 10V tTHL 15V tTHL LOAD CAPACITANCE (CL) (pF) 0 102030405060708090 100 0 80 70 60 50 40 30 20 10 AMBIENT TEMPERATURE (TA) = +25 oC RL = 120 Ω TO VDD SUPPLY VOLTAGE (VDD) = 5V tPLH, tPHL 10V tPLH 15V tPLH 15V tPHL LOAD CAPACITANCE (CL) (pF) 10 20 30 40 50 60 70 80 90 100 10V tPHL 25 50 75 100 125 150 175 10V TPHL |
Similar Part No. - CD40107 |
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Similar Description - CD40107 |
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