AD7769

–11–

REV. A

where A is the peak amplitude of the sine wave and p (V) the

probability of occurrence at a voltage V. The histogram plot of

Figure 17 corresponds very well with this shape.

Figure 17. ADC Histogram Plot

In digital signal processing applications, where the AD7769 is

used to sample ac signals, it is essential that the signal sampling

occurs at exactly equal intervals. This minimizes errors due to

sampling uncertainty or jitter. A precise timer or clock source,

to start the conversion process, is the best method of generating

equidistant sampling intervals.

MICROPROCESSOR/MICROCOMPUTER INTERFACING

The AD7769 is designed for easy interfacing to microprocessors

and microcomputers as a memory mapped peripheral or an I/O

device. In addition, the AD7769 high speed bus timing allows

direct interfacing to many DSP processors such as the

TMS320C10 and ADSP-2101.

AD7769–TMS320C10 Interface

A typical interface to the TMS320C10 is shown in Figure 18.

The AD7769 is mapped at a port address, and the interface is

designed for the maximum TMS320C10 clock frequency of

20 MHz.

Figure 18. AD7769 to TMS320C10 Interface

This is for an ideal part with no differential or integral linearity

errors. These errors will cause a degradation in SNR. By work-

ing backwards from the above equation, it is possible to get a

measure of ADC performance expressed in effective number of

bits (N). The effective number of bits is plotted versus fre-

quency in Figure 15. The effective number of bits typically falls

between 7.7 and 7.9, corresponding to SNR Figures 48.1 and

49.7 dB.

Figure 15. Effective Number of Bits vs. Frequency

Figure 16 shows a spectrum analyzer plot of the output spec-

trum from one of the DACs with an ideal sine wave table loaded

to the data inputs of the DAC. In this case, the SNR is 47 dB.

Figure 16. DAC Output Spectrum

Histogram Plot

taken, it is possible to plot a histogram showing the frequency of

occurrence of each of the 256 ADC codes. If a particular step is

wider than the ideal 1 LSB width, then the code associated with

that step will accumulate more counts than for the code for an

ideal step. Likewise, a step narrower than ideal width will have

fewer counts. Missing codes are easily seen because a missing

code means zero counts for a particular code. The absence of

large spikes in the plot indicates small differential nonlinearity.

Figure 17 shows a histogram plot for the ADC indicating very

small differential nonlinearity and no missing codes for an input

frequency of 204 kHz. For a sine wave input, a perfect ADC

would produce a probability density function described by the

equation:

p (V) =

1