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CA3282AS1 Datasheet(PDF) 9 Page - Intersil Corporation |
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CA3282AS1 Datasheet(HTML) 9 Page - Intersil Corporation |
9 / 10 page 9 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli- able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com CA3282 Single-In-Line Plastic Packages (SIP) D SEE TAB DETAIL E1 TERMINAL #1 TERMINAL N E A L1 L F TYP ALL LEADS TAB DETAIL R1 -Y- -Z- 3 e2 -X- e1 e B 0.010(0.25) Z X M M Y M 0.024(0.61) Z M C E2 ØP Ø 0.015(0.38) Z X M S NOTES: 1. Refer to series symbol list, JEDEC Publication No. 95. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1982. 3. N is the number of terminals. 4. Controlling dimension: INCH. HL H H H H H H H H L L L L L L L e3 Z15.05A (JEDEC MO-048 AB ISSUE A) 15 LEAD PLASTIC SINGLE-IN-LINE PACKAGE STAGGERED VERTICAL LEAD FORM SYMBOL INCHES MILLIMETERS MIN MAX MIN MAX A 0.172 0.182 4.37 4.62 B 0.024 0.031 0.61 0.79 C 0.014 0.024 0.36 0.61 D 0.778 0.798 19.76 20.27 E 0.684 0.694 17.37 17.63 E1 0.416 0.426 10.57 10.82 E2 0.110 BSC 2.79 BSC e 0.050 BSC 1.27 BSC e1 0.200 BSC 5.08 BSC e2 0.169 BSC 4.29 BSC e3 0.700 BSC 17.78 BSC F 0.057 0.063 1.45 1.60 L 0.150 0.176 3.81 4.47 L1 0.690 0.710 17.53 18.03 N15 15 ØP 0.148 0.152 3.76 3.86 R1 0.065 0.080 1.65 2.03 Rev. 1 4/98 |
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