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TOP264-271 Datasheet(PDF) 6 Page - Power Integrations, Inc. |
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TOP264-271 Datasheet(HTML) 6 Page - Power Integrations, Inc. |
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6 / 40 page  Rev. E 08/12 6 TOP264-271 www.powerint.com Figure 7. Switching Frequency Jitter (Idealized V DRAIN Waveforms). f OSC - 4 ms Time Switching Frequency VDRAIN f OSC + modes. Please see the following sections for the details of the operation of each mode and the transitions between modes. Full Frequency PWM mode: The PWM modulator enters full frequency PWM mode when the CONTROL pin current (I C) reaches I B. In this mode, the average switching frequency is kept constant at f OSC (pin selectable 132 kHz or 66 kHz). Duty cycle is reduced from DC MAX through the reduction of the on-time when I C is increased beyond IB. This operation is identical to the PWM control of all other TOPSwitch families. TOP264-271 only operates in this mode if the cycle-by-cycle peak drain current stays above k PS(UPPER) × ILIMIT(set), where kPS(UPPER) is 55% (typical) and I LIMIT(set) is the current limit externally set via the EXTERNAL CURRENT LIMIT (X) pin. Variable Frequency PWM mode: When peak drain current is lowered to k PS(UPPER) × ILIMIT(set) as a result of power supply load reduction, the PWM modulator initiates the transition to variable frequency PWM mode, and gradually turns off frequency jitter. In this mode, peak drain current is held constant at k PS(UPPER) × I LIMIT(set) while switching frequency drops from the initial full frequency of f OSC (132 kHz or 66 kHz) towards the minimum frequency of f MCM(MIN) (30 kHz typical). Duty cycle reduction is accomplished by extending the off-time. Low Frequency PWM mode: When switching frequency reaches f MCM(MIN) (30 kHz typical), the PWM modulator starts to transition to low frequency mode. In this mode, switching frequency is held constant at f MCM(MIN) and duty cycle is reduced, similar to the full frequency PWM mode, through the reduction of the on-time. Peak drain current decreases from the initial value of k PS(UPPER) × ILIMIT(set) towards the minimum value of k PS(LOWER) × ILIMIT(set), where kPS(LOWER) is 25% (typical) and ILIMIT(set) is the current limit externally set via the X pin. Multi-Cycle-Modulation mode: When peak drain current is lowered to k PS(LOWER) × ILIMIT(set), the modulator transitions to multi-cycle-modulation mode. In this mode, at each turn-on, the modulator enables output switching for a period of T MCM(MIN) at the switching frequency of f MCM(MIN) (4 or 5 consecutive pulses at 30 kHz) with the peak drain current of k PS(LOWER) × ILIMIT(set), and stays off until the CONTROL pin current falls below I C(OFF). This mode of operation not only keeps peak drain current low but also minimizes harmonic frequencies between 6 kHz and 30 kHz. By avoiding transformer resonant frequency this way, all potential transformer audible noises are greatly suppressed. Maximum Duty Cycle The maximum duty cycle, DC MAX, is set at a default maximum value of 78% (typical). However, by connecting the VOLTAGE- MONITOR to the rectified DC high-voltage bus through a resistor with appropriate value (4 M W typical), the maximum duty cycle can be made to decrease from 78% to 40% (typical) when input line voltage increases from 88 V to 380 V, with dual gain slopes. Error Amplifier The shunt regulator can also perform the function of an error amplifier in primary-side feedback applications. The shunt regulator voltage is accurately derived from a temperature- compensated bandgap reference. The CONTROL pin dynamic impedance Z C sets the gain of the error amplifier. The CONTROL pin clamps external circuit signals to the V C voltage level. The CONTROL pin current in excess of the supply current is separated by the shunt regulator and becomes the feedback current I FB for the pulse width modulator. On-Chip Current Limit with External Programmability The cycle-by-cycle peak drain current limit circuit uses the output MOSFET ON-resistance as a sense resistor. A current limit comparator compares the output MOSFET ON-state drain to source voltage V DS(ON) with a threshold voltage. High drain current causes V DS(ON) to exceed the threshold voltage and turns the output MOSFET off until the start of the next clock cycle. The current limit comparator threshold voltage is temperature compensated to minimize the variation of the current limit due to temperature related changes in R DS(ON) of the output MOSFET. The default current limit of TOP264-271 is preset internally. However, with a resistor connected between EXTERNAL CURRENT LIMIT (X) pin and SOURCE pin, current limit can be programmed externally to a lower level between 30% and 100% of the default current limit. By setting current limit low, a larger TOP264-271 than necessary for the power required can be used to take advantage of the lower R DS(ON) for higher efficiency/ smaller heat sinking requirements. With a second resistor connected between the EXTERNAL CURRENT LIMIT (X) pin and the rectified DC high-voltage bus, the current limit is reduced with increasing line voltage, allowing a true power limiting operation against line variation to be implemented. When using an RCD clamp, this power limiting technique reduces maximum clamp voltage at high-line. This allows for higher reflected voltage designs as well as reducing clamp dissipation. The leading edge blanking circuit inhibits the current limit comparator for a short time after the output MOSFET is turned on. The leading edge blanking time has been set so that, if a power supply is designed properly, current spikes caused by primary-side capacitances and secondary-side rectifier reverse recovery time should not cause premature termination of the switching pulse. The current limit is lower for a short period after the leading edge blanking time. This is due to dynamic characteristics of the MOSFET. During start-up and fault conditions the controller prevents excessive drain currents by reducing the switching frequency. Line Undervoltage Detection (UV) At power-up, UV keeps TOP264-271 off until the input line voltage reaches the undervoltage threshold. At power-down, |
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