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ACS573HMSR Datasheet(PDF) 1 Page - Intersil Corporation |
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ACS573HMSR Datasheet(HTML) 1 Page - Intersil Corporation |
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1 / 4 page  1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 ACS573MS Radiation Hardened Octal Three-State Transparent Latch Pinouts 20 LEAD CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C TOP VIEW 20 LEAD CERAMIC FLATPACK MIL-STD-1835 DESIGNATOR, CDFP4-F20, LEAD FINISH C TOP VIEW 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 OE D0 D1 D2 D3 D4 D6 D5 D7 GND VCC Q1 Q2 Q3 Q0 Q4 Q5 Q6 Q7 LE 2 3 4 5 6 7 8 120 19 18 17 16 15 14 13 9 10 12 11 OE D0 D1 D2 D3 D4 D6 D5 D7 GND VCC Q1 Q2 Q3 Q0 Q4 Q5 Q6 Q7 LE Features • Devices QML Qualified in Accordance with MIL-PRF-38535 • Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96724 and Intersil’s QM Plan • 1.25 Micron Radiation Hardened SOS CMOS • Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si) • Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day (Typ) • SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg • Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse • Dose Rate Survivability . . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse • Latch-Up Free Under Any Conditions • Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC • Significant Power Reduction Compared to ALSTTL Logic • DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V • Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min • Input Current ≤ 1µA at VOL, VOH • Fast Propagation Delay . . . . . . . . . . . . . . . . 17ns (Max), 12ns (Typ) Description The Intersil ACS573MS is a Radiation Hardened Octal Transparent Latch with an active low output enable. The outputs are transparent to the inputs when the latch enable (LE) is High. When the latch goes low the data is latched. The output enable controls the three-state outputs. When the output enable pins (OE) are high the output is in a high impedance state. The latch operation is independent of the state of output enable. The ACS573MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened, high-speed, CMOS/SOS Logic family. The ACS573MS is supplied in a 20 lead Ceramic Flatpack (K suffix) or a Ordering Information PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE 5962F9672401VRC -55oC to +125oC MIL-PRF-38535 Class V 20 Lead SBDIP 5962F9672401VXC -55oC to +125oC MIL-PRF-38535 Class V 20 Lead Ceramic Flatpack ACS573D/Sample 25oC Sample 20 Lead SBDIP ACS573K/Sample 25oC Sample 20 Lead Ceramic Flatpack ACS573HMSR 25oC Die Die January 1996 Spec Number 518893 File Number 4093 |
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