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ACS373MS Datasheet(PDF) 1 Page - Intersil Corporation |
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ACS373MS Datasheet(HTML) 1 Page - Intersil Corporation |
1 / 10 page 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 ACS373MS Radiation Hardened Octal Transparent Latch, Three-State Pinouts 20 LEAD CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C TOP VIEW 20 LEAD CERAMIC FLATPACK MIL-STD-1835 DESIGNATOR, CDFP4-F20, LEAD FINISH C TOP VIEW 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 OE Q0 D0 D1 Q1 Q2 D3 D2 Q3 GND VCC D7 D6 Q6 Q7 Q5 D5 D4 Q4 LE 2 3 4 5 6 7 8 120 19 18 17 16 15 14 13 OE Q0 D0 D1 Q1 Q2 D2 D3 9 10 12 11 Q3 GND VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 LE April 1995 Spec Number 518799 File Number 3999 Truth Table OE LE D Q L HHH LHL L LL I L LLh H HX X Z NOTE: L = Low Voltage Level H = High Voltage Level X = Don’t Care Z = High Impedance State I = Low voltage level one set-up time prior to the high to low latch enable transition h = High voltage level one set-up time prior to the high to low latch enable transition Functional Diagram DQ LE D LE Q OE LATCH COMMON OE 1 OF 8 (3, 4, 7, 8, 13, 14, 17, 18) (2, 5, 6, 9, 12, 15, 16, 19) (1) (11) CONTROLS Ordering Information PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE ACS373DMSR -55oC to +125oC Intersil Class S Equivalent 20 Lead SBDIP ACS373KMSR -55oC to +125oC Intersil Class S Equivalent 20 Lead Ceramic Flatpack ACS373D/Sample +25oC Sample 20 Lead SBDIP ACS373K/Sample +25oC Sample 20 Lead Ceramic Flatpack ACS373HMSR +25oC Die Die Features • 1.25 Micron Radiation Hardened SOS CMOS • Total Dose 300K RAD (Si) • Single Event Upset (SEU) Immunity <1 x 10-10 Errors/Bit-Day (Typ) • SEU LET Threshold >80 MEV-cm2/mg • Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse • Latch-Up Free Under Any Conditions • Military Temperature Range: -55oC to +125oC • Significant Power Reduction Compared to ALSTTL Logic • DC Operating Voltage Range: 4.5V to 5.5V • Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min • Input Current ≤1µA at VOL, VOH Description The Intersil ACS373MS is a radiation hardened octal transparent latch with three-state outputs. The outputs are transparent to the inputs when the latch enable (LE) is high. When the LE goes low, the data is latched. When the Output Enable (OE) is high, the outputs are in the high impedance state. The latch operation is independent of the state of the output enable. The ACS373MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of the radiation hardened, high-speed, CMOS/SOS Logic Family. |
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