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CP82C59A-12 Datasheet(PDF) 10 Page - Intersil Corporation |
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CP82C59A-12 Datasheet(HTML) 10 Page - Intersil Corporation |
10 / 20 page 4-10 immediately before returning from the service routine, or if the AEOI (Automatic End of Interrupt) bit is set, until the trail- ing edge of the last INTA. While the IS bit is set, all further interrupts of the same or lower priority are inhibited, while higher levels will generate an interrupt (which will be acknowledged only if the microprocessor internal interrupt enable flip-flop has been re-enabled through software). After the initialization sequence, IR0 has the highest priority and IR7 the lowest. Priorities can be changed, as will be explained in the rotating priority mode or via the set priority command. D7 A0 D6 D5 D4 D3 D2 D1 D0 1M7 M6 M5 M3 M2 M1 M0 M4 OCW1 Interrupt Mask 1 = Mask set 0 = Mask reset D7 A0 D6 D5 D4 D3 D2 D1 D0 0 R SL EOI 0 L2 L1 L0 0 OCW2 IR LEVEL TO BE 01 5 23 4 6 7 01 1 01 0 0 1 00 0 11 0 1 1 00 1 00 1 1 1 00 1 01 1 10 1 10 0 0 1 1 0 0 1 1 10 0 1 0 Non-specific EOI command Specific EOI command Rotate on non-specific EOI command Rotate in automatic EOI mode (set) Rotate in automatic EOI mode (clear) Rotate on specific EOI command Set priority command No operation † † † ACTED UPON End of interrupt Automatic rotation Specific rotation † L0 - L2 are used D7 A0 D6 D5 D4 D3 D2 D1 D0 0 0 ESMM SMM 1 P RR RIS 0 OCW3 00 11 1 1 0 0 No Action Read IR reg on next RD pulse Read IS reg on next RD pulse 1 = Poll command 0 = No poll command 00 11 1 1 0 0 No Action Reset special mask Set special mask READ REGISTER COMMAND FIGURE 8. 82C59A OPERATION COMMAND WORD FORMAT SPECIAL MASK MODE 82C59A |
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