4-353

SYMBOL

PARAMETER

MIN

MAX

UNIT

TEST CONDITIONS

(1)

TCLCL

CLK Cycle Period

125

-

ns

Note 3

(2)

TCLCH

CLK Low Time

55

-

ns

Note 3

(3)

TCHCL

CLK High Time

35

-

ns

Note 3

(4)

TSVCH

Status Active Setup

65

TCLCL-10

ns

Note 3

(5)

TSHCL

Status Inactive Setup

50

TCLCL-10

ns

Note 3

(6)

THVCH

Status Inactive Hold

10

-

ns

Note 3

(7)

THVCL

Status Active Hold

10

-

ns

Note 3

(8)

TBYSBL

BUSY

↓↑ Setup to BCLK↓

20

-

ns

Note 3

(9)

TCBSBL

CBRQ

↓↑ Setup to BCLK↓

20

-

ns

Note 3

(10)

TBLBL

BCLK Cycle Time

100

-

ns

Note 3

(11)

TBHCL

BCLK High Time

30

0.65

(TBLBL)

ns

Note 3

(12)

TCLLL1

LOCK Inactive Hold

10

-

ns

Note 3

(13)

TCLLL2

LOCK Active Setup

40

-

ns

Note 3

(14)

TPNBL

BPRN

↓↑ to BCLK Setup Time

20

-

ns

Note 3

(15)

TCLSR1

SYSB/RESB Setup

0

-

ns

Note 3

(16)

TCLSR2

SYSB/RESB Hold

30

-

ns

Note 3

(17)

TIVIH

Initialization Pulse Width

675

-

ns

Note 3

(18)

TBLBRL

BCLK to BREQ Delay

↓↑

-

35

ns

Note 3

(19)

TBLPOH

BCLK to BPRO

↓↑

-

35

ns

Note 1 and 3

(20)

TPNPO

BPRN

↓↑ to BPRO↓↑ Delay

-

22

ns

Note 1 and 3

(21)

TBLBYL

BCLK to BUSY Low

-

60

ns

Note 3

(22)

TBLBYH

BCLK to BUSY Float

-

35

ns

Note 2 and 3

(23)

TCLAEH

CLK to AEN High

-

65

ns

Note 3

(24)

TBLAEL

BCLK to AEN Low

-

40

ns

Note 3

(25)

TBLCBL

BCLK to CBRQ Low

-

60

ns

Note 3

(26)

TBLCBH

BCLK to CBRQ Float

-

40

ns

Note 2 and 3

(27)

TOLOH

Output Rise Time

-

20

ns

From 0.8V to 2.0V, Note 4

(28)

TOHOL

Output Fall Time

-

12

ns

From 2.0V to 0.8V, Note 4

(29)

TILIH

Input Rise Time

-

20

ns

From 0.8V to 2.0V

(30)

TIHIL

Input Fall Time

-

20

ns

From 2.0V to 0.8V

NOTES:

1. BCLK generates the first BPRO wherein subsequent BPRO changes lower in the chain are generated through BPRON.

2. Measured at 0.5V above GND.

3. All AC parameters tested as per AC test load circuits. Input rise and fall times are driven at 1ns/V.

4. Except BUSY and CBRQ

82C89