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CD82C89 Datasheet(PDF) 4 Page - Intersil Corporation |
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CD82C89 Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 15 page 4-346 Functional Description The 82C89 Bus Arbiter operates in conjunction with the 82C88 Bus Controller to interface 80C86, 80C88 processors to a multi-master system bus (both the 80C86 and 80C88 are configured in their max mode). The processor is unaware of the arbiter’s existence and issues commands as though it has exclusive use of the system bus. If the proces- sor does not have the use of the multi-master system bus, the arbiter prevents the Bus Controller (82C88), the data transceivers and the address latches from accessing the system bus (e.g. all bus driver outputs are forced into the high impedance state). Since the command sequence was not issued by the 82C88, the system bus will appear as “Not Ready” and the processor will enter wait states. The proces- sor will remain in Wait until the Bus Arbiter acquires the use of the multi-master system bus whereupon the arbiter will allow the bus controller, the data transceivers, and the address latches to access the system. Typically, once the command has been issued and a data transfer has taken place, a transfer acknowledge (XACK) is returned to the pro- cessor to indicate “READY” from the accessed slave device. The processor then completes its transfer cycle. Thus the arbiter serves to multiplex a processor (or bus master) onto a multi-master system bus and avoid contention problems between bus masters. Arbitration Between Bus Masters In general, higher priority masters obtain the bus when a lower priority master completes its present transfer cycle. Lower priority bus masters obtain the bus when a higher pri- ority master is not accessing the system bus. A strapping option (ANYRQST) is provided to allow the arbiter to surren- der the bus to a lower priority master as though it were a master of higher priority. If there are no other bus masters requesting the bus, the arbiter maintains the bus so long as its processor has not entered the HALT State. The arbiter will not voluntarily surrender the system bus and has to be forced off by another master’s bus request, the HALT State being the only exception. Additional strapping options permit other modes of operation wherein the multi-master system bus is surrendered or requested under different sets of conditions. Priority Resolving Techniques Since there can be many bus masters on a multi-master sys- tem bus, some means of resolving priority between bus masters simultaneously requesting the bus must be pro- vided. The 82C89 Bus Arbiter provides several resolving techniques. All the techniques are based on a priority con- cept that at a given time one bus master will have priority above all the rest. There are provisions for using parallel pri- ority resolving techniques, serial priority resolving tech- niques, and rotating priority techniques. Parallel Priority Resolving The parallel priority resolving technique uses a separate bus request line BREQ for each arbiter on the multi-master sys- tem bus, see Figure 1. Each BREQ line enters into a priority encoder which generates the binary address of the highest priority BREQ line which is active. The binary address is decoded by a decoder to select the corresponding BPRN (Bus Priority In) line to be returned to the highest priority requesting arbiter. The arbiter receiving priority (BPRN true) then allows its associated bus master onto the multi-master system bus as soon as it becomes available (i.e., the bus is no longer busy). When one bus arbiter gains priority over another arbiter it cannot immediately seize the bus, it must wait until the present bus transaction is complete. Upon completing its transaction the present bus occupant recog- nizes that it no longer has priority and surrenders the bus by releasing BUSY. BUSY is an active low “OR” tied signal line which goes to every bus arbiter on the system bus. When BUSY goes inactive (high), the arbiter which presently has bus priority (BPRN true) then seizes the bus and pulls BUSY low to keep other arbiters off of the bus. See waveform tim- ing diagram, Figure 2. Note that all multimaster system bus transactions are synchronized to the bus clock (BCLK). This allows the parallel priority resolving circuitry or any other pri- ority resolving scheme employed to settle. FIGURE 1. PARALLEL PRIORITY RESOLVING TECHNIQUE FIGURE 2. HIGHER PRIORITY ARBITER OBTAINING THE BUS FROM A LOWER PRIORITY ARBITER NOTES: 1. Higher priority bus arbiter requests the Multi-Master system bus. 2. Attains priority. 3. Lower priority bus arbiter releases BUSY. 4. Higher priority bus arbiter then acquires the bus and pulls BUSY down. BUS ARBITER 1 BUS ARBITER 2 BUS ARBITER 3 BUS ARBITER 4 74HC148 PRIORITY ENCODER 74HC138 3 TO 8 ENCODER • • • • BREQ BPRN BREQ BPRN BREQ BPRN BREQ BPRN BCLK BREQ BPRN BUSY 1 2 3 4 82C89 |
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