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AD7011 Datasheet(PDF) 4 Page - Analog Devices |
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AD7011 Datasheet(HTML) 4 Page - Analog Devices |
4 / 12 page AD7011 REV. B –4– TRANSMIT SECTION TIMING Parameter Limit at TA = –40 C to +85 C Units Description t4 10 ns min Power Setup Time. t1 – 10 ns max t5 4097t1 + 70 ns max MCLK rising edge, after Power high, to READY rising edge. t6 10 ns min BIN Setup Time. t1 – 10 ns max t7 t1 + 70 ns max MCLK to READY propagation delay. t8 3t1 + 70 ns MCLK rising edge, after BIN high, to first TxCLK rising edge. t9 64t1 ns TxCLK Cycle Time. t10 32t1 ns TxCLK High Time. t11 32t1 ns TxCLK Low Time. t12 50 ns min TxCLK falling edge to TxDATA setup time. t13 0 ns min TxCLK falling edge to TxDATA hold time. t14 3t1 ns max BIN low setup to Last transmitted symbol after ramp down. t15 124t1 ns max BIN low hold to Last transmitted symbol after ramp down. t16 7.5t9 ns Ramp Down cycle time after the last transmitted symbol. t17 30t1 ns max Last TxCLK falling edge to READY rising edge. t18 10 ns max Digital Output Rise Time. t19 10 ns max Digital Output Fall Time. MCLK READY BIN TxCLK TxDATA Y k t 4 t 5 t 7 t 9 t 10 t 11 t 12 t 13 t 8 t 6 X k POWER Figure 4. Transmit Timing at the Start of a Tx Burst MCLK READY BIN TxCLK TxDATA t 14 X N+4 Y N+4 X N+5 Y N+8 X N+8 t 17 POWER t 15 t 16 Figure 5. Transmit Timing at the End of a Tx Burst (VAA = VDD = +5 V 10%; AGND = DGND = 0 V, fMCLK = 3.1104 MHz. All specifications are TMIN to TMAX unless otherwise noted.) |
Similar Part No. - AD7011_15 |
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Similar Description - AD7011_15 |
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