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IP82C50A-5 Datasheet(PDF) 11 Page - Intersil Corporation |
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IP82C50A-5 Datasheet(HTML) 11 Page - Intersil Corporation |
11 / 21 page 11 TRANSMITTER HOLDING REGISTER (THR) The Transmitter Holding Register (THR) holds parallel data from the data bus (D0-D7) until the Transmitter Shift Register is empty and ready to accept a new character for transmis- sion. The transmitter and receiver word length and number of stop bits are the same. If the character is less than eight bits, unused bits at the microprocessor data bus are ignored by the transmitter. Data Bit 0 (THR(0)) is the first serial data bit transmitted. The THRE flag (LSR(5)) reflect the status of the THR. The TEMT flag (LSR(6)) indicates if both the THR and TSR are empty. SCRATCHPAD REGISTER (SCR) This 8-bit Read/Write register has no effect on the 82C50A. It is intended as a scratchpad register to be used by the pro- grammer to hold data temporarily. Interrupt Structure INTERRUPT IDENTIFICATION REGISTER (IIR) The 82C50A has interrupt capability for interfacing to current microprocessors. In order to minimize software overhead during data character transfers, the 82C50A prioritizes interrupts into four levels. The four levels of interrupt condi- tions are as follows: 1. Receiver Line Status (Priority 1) 2. Received Data Ready (Priority 2) 3. Transmitter Holding Register Empty (Priority 3) 4. Modem Status (Priority 4). Information indicating that a prioritized interrupt is pending and the type of interrupt is stored in the Interrupt Identifica- tion Register (IIR). When addressed during chip select time, the lIR indicates the highest priority interrupt pending. No other interrupts are acknowledged until the interrupt is ser- viced by the CPU. The contents of the lIR are indicated in Table 2 and are described below. IIR(0): IIR(0) can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pend- ing. When IIR(0) is low, an interrupt is pending, and the lIR contents may be used as a pointer to the appropriate inter- rupt service routine. When lIR(0) is high, no interrupt is pending. IlR(1) and IIR(2): llR(1) and IlR(2) are used to identify the highest priority interrupt pending as indicated in Table 2. lIR(3) - IIR(7): These five bits of the lIR are logic 0. INTERRUPT ENABLE REGISTER (IER) The Interrupt Enable Register (IER) is a Write register used to independently enable the four 82C50A interrupts which activate the interrupt (lNTRPT) output. All interrupts are dis- abled by resetting IER(0) - IER(3) of the Interrupt Enable Register. Interrupts are enabled by setting the appropriate bits of the IER high. Disabling the interrupt system inhibits the Interrupt Identification Register and the active (high) INTRPT output. All other system functions operate in their normal manner, including the setting of the Line Status and THR Bits 0 thru 7 THR (0) Data Bit 0 THR (1) Data Bit 1 THR (2) Data Bit 2 THR (3) Data Bit 3 THR (4) Data Bit 4 THR (5) Data Bit 5 THR (6) Data Bit 6 THR (7) Data Bit 7 SCR Bits 0 thru 7 SCR (0) Data Bit 0 SCR (1) Data Bit 1 SCR (2) Data Bit 2 SCR (3) Data Bit 3 SOR (4) Data Bit 4 SCR (5) Data Bit 5 SOR (6) Data Bit 6 SCR (7) Data Bit 7 TABLE 2. INTERRUPT IDENTIFICATION REGISTER INTERRUPT IDENTIFICATION INTERRUPT SET AND RESET FUNCTIONS BIT 2 BIT 1 BIT 0 PRIORITY LEVEL INTERRUPT FLAG INTERRUPT SOURCE INTERRUPT RESET CONTROL X X 1 None None 1 1 0 First Receiver Line Status OE, PE, FE, or BI LSR Read 1 0 0 Second Received Data Available Receiver Data Available RBR Read 0 1 0 Third THRE THRE IIR Read if THRE is the Interrupt Source or THR Write 0 0 0 Fourth Modem Status CTS, DSR, RI, DCD MSR Read NOTE: X = Not Defined, May Be 0 or 1 82C50A |
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