Electronic Components Datasheet Search |
|
AD6620 Datasheet(PDF) 7 Page - Analog Devices |
|
AD6620 Datasheet(HTML) 7 Page - Analog Devices |
7 / 44 page AD6620 –7– REV. A TIMING DIAGRAMS CLK, INPUTS, PARALLEL OUTPUTS RESET with PAR/SER = “1” establishes Parallel Outputs active. tCLKH tCLKL tCLK CLK Figure 3. CLK Timing Requirements CLK IN[15:0] EXP[2:0] A/B tSI tHI DATA Figure 4. Input Data Timing Requirements CLK OUT[15:0] VALID OUTPUT DATA DVOUT I/QOUT tDPR tDPF I Q I Q IA QA IB QB tDPF Figure 5. Parallel Output Switching Characteristics SYNC PULSES: SLAVE OR MASTER tSY tHY CLK SYNC NCO SYNC CIC SYNC RCF NOTE: IN THE SLAVE MODE WITH SINGLE CHANNEL OPERATION, THE WIDTH OF THE SYNC_NCO SHOULD BE ONE SAMPLE CLOCK CYCLE. IN DUAL CHANNEL MODE, THE PULSEWIDTH SHOULD BE TWO SAMPLE CLOCK CYCLES. IF A PULSE LONGER THAN SPECIFIED IS USED, THE NCO WILL BE INHIBITED AND NOT INCREMENT PROPERLY. Figure 6. SYNC Slave Timing Requirements CLK tCHP tCPL tCS tCH IN[15:0] E[2:0] A/B N+1 N tCLK Figure 7. SYNC Master Delay tRESL RESET Figure 8. Reset Timing Requirements |
Similar Part No. - AD6620_15 |
|
Similar Description - AD6620_15 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |