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AD5531 Datasheet(PDF) 5 Page - Analog Devices |
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AD5531 Datasheet(HTML) 5 Page - Analog Devices |
5 / 20 page AD5530/AD5531 Rev. B | Page 5 of 20 AC PERFORMANCE CHARACTERISTICS VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter B Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 20 μs typ Full-scale change to ±½ LSB. DAC latch contents alternately loaded with all 0s and all 1s. Slew Rate 1.3 V/μs typ Digital-to-Analog Glitch Impulse 120 nV-s typ DAC latch alternately loaded with 0x0FFF and 0x1000. Not dependent on load conditions. Digital Feedthrough 0.5 nV-s typ Effect of input bus activity on DAC output under test. Output Noise Spectral Density @ 1 kHz 100 nV/√Hz typ All 1s loaded to DAC. STANDALONE TIMING CHARACTERISTICS VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter Limit at TMIN, TMAX Unit Description 1 , 2 fMAX 7 MHz max SCLK frequency t1 140 ns min SCLK cycle time t2 60 ns min SCLK low time t3 60 ns min SCLK high time t4 50 ns min SYNC to SCLK falling edge setup time t5 40 ns min SCLK falling edge to SYNC rising edge t6 50 ns min Min SYNC high time t7 40 ns min Data setup time t8 15 ns min Data hold time t9 5 ns min SYNC high to LDAC low t10 50 ns min LDAC pulse width t11 5 ns min LDAC high to SYNC low t12 50 ns min CLR pulse width 1 Guaranteed by design, not subject to production test. 2 Sample tested during initial release and after any redesign or process change that can affect this parameter. All input signals are measured with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. SCLK SYNC SDIN MSB DB15 DB14 DB11 DB0 LSB t1 t3 t2 t5 t4 t6 t7 t8 t9 t10 t11 t12 LDAC1 CLR 1LDAC CAN BE TIED PERMANENTLY LOW, IF REQUIRED. Figure 2. Timing Diagram for Standalone Mode |
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Similar Description - AD5531_15 |
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