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87C196KT Datasheet(PDF) 4 Page - Intel Corporation

Part No. 87C196KT
Description  ADVANCED 16-BIT CHMOS MICROCONTROLLER
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Maker  INTEL [Intel Corporation]
Homepage  http://www.intel.com
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87C196KT87C196KS
PIN DESCRIPTIONS
Symbol
Name and Function
VCC
Main supply voltage (a5V)
VSS VSSI VSSI
Digital circuit ground (0V) There are three VSS pins all of which MUST be connected
VREF
Reference for the AD converter (a5V) VREF is also the supply voltage to the analog
portion of the AD converter and the logic used to read Port 0 Must be connected for
AD and Port 0 to function
VPP
Programming voltage for the EPROM parts It should be a125V for programming It
is also the timing pin for the return from powerdown circuit Connect this pin with a
1 mF capacitor to VSS anda1MX resistor to VCC If this function is not used VPP
may be tied to VCC
ANGND
Reference ground for the AD converter Must be held at nominally the same
potential as VSS
XTAL1
Input of the oscillator inverter and the internal clock generator
XTAL2
Output of the oscillator inverter
P27CLKOUT
Output of the internal clock generator The frequency is
the oscillator frequency It
has a 50% duty cycle Also LSIO pin
RESET
Reset input to the chip Input low for at least 16 state times will reset the chip The
subsequent low to high transition resynchronizes CLKOUT and commences a 10-
state time sequence in which the PSW is cleared bytes are read from 2018H and
201AH loading the CCBs and a jump to location 2080H is executed Input high for
normal operation RESET has an internal pullup
P57BUSWIDTH
Input for bus width selection If CCR bit 1 is a one and CCR1 bit 2 is a one this pin
dyamically controls the Buswidth of the bus cycle in progress If BUSWIDTH is low an
8-bit cycle occurs if BUSWIDTH is high a 16-bit cycle occurs If CCR bit 1 is ‘‘0’’ and
CCR1 bit 2 is ‘‘1’’ all bus cycles are 8-bit if CCR bit 1 is ‘‘1’’ and CCR1 bit 2 is ‘‘0’’ all
bus cycles are 16-bit CCR bit 1 e ‘‘0’’ and CCR1 bit 2 e ‘‘0’’ is illegal Also an LSIO
pin when not used as BUSWIDTH
NMI
A positive transition causes a non maskable interrupt vector through memory location
203EH
P51INST
Output high during an external memory read indicates the read is an instruction fetch
INST is valid throughout the bus cycle INST is active only during external memory
fetches during internal EPROM fetches INST is held low Also LSIO when not INST
EA
Input for memory select (External Access) EA equal to a high causes memory
accesses to locations 2000H through 9FFFH to be directed to on-chip EPROMROM
EA equal to a low causes accesses to these locations to be directed to off-chip
memory EA ea125V causes execution to begin in the Programming Mode EA is
latched at reset
P50ALEADV
Address Latch Enable or Address Valid output as selected by CCR Both pin options
provide a latch to demultiplex the address from the addressdata bus When the pin is
ADV it goes inactive (high) at the end of the bus cycle ADV can be used as a chip
select for external memory ALEADV is active only during external memory
accesses Also LSIO when not used as ALE
P53RD
Read signal output to external memory RD is active only during external memory
reads or LSIO when not used as RD
P52WR WRL
Write and Write Low output to external memory as selected by the CCR WR will go
low for every external write while WRL will go low only for external writes where an
even byte is being written WR WRL is active during external memory writes Also an
LSIO pin when not used as WR WRL
4
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