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87C196KR Datasheet(PDF) 2 Page - Intel Corporation |
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87C196KR Datasheet(HTML) 2 Page - Intel Corporation |
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2 / 25 page  87C196KRKQ 87C196JVJT 87C196JRJQ The MCS 96 microcontroller family members are all high performance microcontrollers with a 16-bit CPU The 87C196KxJx family members listed above are composed of the high-speed (16 MHz) core as well as the following peripherals up to 48 Kbytes of Programmable EPROM up to 15 Kbytes of Register RAM 512 bytes of code RAM (16-bit addressing modes) with the ability to execute from this RAM space an eight channel-10-Bit g3 LSB analog to digital converter with programmable SH times with conversion times k5 ms at 16 MHz an asynchronoussynchronous serial IO port (8096 compatible) with a dedicated 16-bit baud rate gener- ator an additional synchronous serial IO port (8096 compatible) with a dedicated 16-bit baud rate gener- ator an additional synchronous serial IO port with full duplex masterslave transceivers a flexible tim- ercounter structure with prescaler cascading and quadrature capabilities 10 modularized multiplexed high speed IO for capture and compare (called Event Processor Array) with 250 ns resolution and double buffered inputs a sophisticated prioritized in- terrupt structure with programmable Peripheral Transaction Server (PTS) The PTS has several channel modes including singleburst block trans- fers from any memory location to any memory loca- tion a PWM and PWM toggle mode to be used in conjunction with the EPA and an AD scan mode Additional SFR space is allocated for the EPA and can be ‘‘windowed’’ into the lower Register RAM area Please refer to the following datasheets for higher frequency versions of devices contained within this datasheet 20 MHz 87C196JT Order 272529 20 MHz 87C196JV Order Number 272580 ARCHITECTURE The 87C196KRKQJVJTJRJQ are members of the MCS 96 microcontroller family has the same ar- chitecture and uses the same instruction set as the 80C196KBKC Many new features have been add- ed including CPU FEATURES Powerdown and Idle Modes 16 MHz Operating Frequency A High Performance Peripheral Transaction Serv- er (PTS) Up to 37 Interrupt Vectors Up to 512 Bytes of Code RAM Up to 15 Kbytes of Register RAM ‘‘Windowing’’ Allows 8-Bit Addressing to Some 16-Bit Addresses 175 ms 16 x 16 Multiply 3 ms 3216 Divide Oscillator Fail Detect PERIPHERAL FEATURES Programmable AD Conversion and SH Times 10 CaptureCompare IO with 2 Flexible Timers Synchronous Serial IO Port for Full Duplex Seri- al IO Total Utilization of ALL Available Pins (IO Mux’d with Control) 2 16-Bit Timers with Prescale Cascading and Quadrature Counting Capabilities Up to 12 Externally Triggered Interrupts NEW INSTRUCTIONS XCHXCHB Exchange the contents of two locations either Word or Byte is supported BMOVi Interruptable Block Move Instruction allows the user to be interrupted during long executing Block Moves TIJMP Table Indirect JUMP This instruction incorporates a way to do complex CASE level branches through one instruction An example of such code savings several interrupt sources and only one interrupt vec- tor The TIJMP instruction will sort through the sources and branch to the appropriate sub-code lev- el in one instruction This instruction was added es- pecially for the EPA structure but has other code saving advantages EPTSDPTS Enable and Disable PTS Interrupts (Works like EI and DI) 2 |
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