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83C196LD Datasheet(PDF) 9 Page - Intel Corporation |
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83C196LD Datasheet(HTML) 9 Page - Intel Corporation |
9 / 22 page ADVANCE INFORMATION 9 AUTOMOTIVE — 83C196LC, 83C196LD T2DIR I Timer 2 External Direction External direction (up/down) for timer 2. Timer 2 increments when T2DIR is high and decrements when it is low. It is also used in conjunction with T2CLK for quadrature counting mode. T2DIR shares a package pin with P1.2 and EPA2. TXD O Transmit Serial Data In serial I/O modes 1, 2, and 3, TXD transmits serial port output data. In mode 0, it is the serial clock output. TXD shares a package pin with P2.0. VCC PWR Digital Supply Voltage Connect each V CC pin to the digital supply voltage. VPP PWR Powerdown Exit V PP causes the device to exit powerdown mode when it is driven low for at least 50 ns. Use this method to exit powerdown only when using an external clock source because it enables the internal phase clocks, but not the internal oscillator. If you do not plan to use the powerdown feature, connect V PP to VCC. VSS GND Digital Circuit Ground These pins supply ground for the digital circuitry. Connect each V SS pin to ground through the lowest possible impedance path. WR# O Write† This active-low output indicates that an external write is occurring. This signal is asserted only during external memory writes. WR# shares a package pin with P5.2 and WRL#. † When this pin is configured as a special-function signal (P5_MODE.2 = 1), the chip configuration register 0 (CCR0) determines whether it functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#. WRL# O Write Low† During 16-bit bus cycles, this active-low output signal is asserted for low-byte writes and word writes to external memory. During 8-bit bus cycles, WRL# is asserted for all write operations. WRL# shares a package pin with P5.2 and WR#. † When this pin is configured as a special-function signal (P5_MODE.2 = 1), the chip configuration register 0 (CCR0) determines whether it functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#. Table 4. Signal Descriptions (Continued) Name Type Description |
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