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83C196LC Datasheet(PDF) 6 Page - Intel Corporation

Part No. 83C196LC
Description  CHMOS 16-BIT MICROCONTROLLER
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Maker  INTEL [Intel Corporation]
Homepage  http://www.intel.com
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6
ADVANCE INFORMATION
83C196LC, 83C196LD — AUTOMOTIVE
3.0
SIGNALS
Table 4. Signal Descriptions
Name
Type
Description
AD15:0
I/O
Address/Data Lines
These pins provide a multiplexed address and data bus. During the address
phase of the bus cycle, address bits 0–15 are presented on the bus and can be
latched using ALE or ADV#. During the data phase, 8- or 16-bit data is
transferred.
AD7:0 share package pins with P3.7:0. AD15:8 share package pins with P4.7:0.
ADV#
O
Address Valid
This active-low output signal is asserted only during external memory
accesses. ADV# indicates that valid address information is available on the
system address/data bus. The signal remains low while a valid bus cycle is in
progress and is returned high as soon as the bus cycle completes.
An external latch can use this signal to demultiplex the address from the
address/data bus. A decoder can also use this signal to generate chip selects
for external memory.
ADV# shares a package pin with P5.0 and ALE.
ALE
O
Address Latch Enable
This active-high output signal is asserted only during external memory cycles.
ALE signals the start of an external bus cycle and indicates that valid address
information is available on the system address/data bus.
An external latch can use this signal to demultiplex the address from the
address/data bus.
CLKOUT
O
Output
Output of the internal clock generator. The CLKOUT frequency is ½ the
oscillator input frequency (F
XTAL
1). CLKOUT has a 50% duty cycle.
CLKOUT shares a package pin with P2.7
EA#
I
External Access
This input determines whether memory accesses to special-purpose and
program memory partitions are directed to internal or external memory. These
accesses are directed to internal memory if EA# is held high and to
externalmemory if EA# is held low. For an access to any other memory location,
the value of EA# is irrelevant.
EA# is sampled and latched only on the rising edge of RESET#. Changing the
level of EA# after reset has no effect.
EPA9:8
EPA3:0
I/O
Event Processor Array (EPA) Capture/Compare Channels
High-speed input/output signals for the EPA capture/compare channels.
The EPA signals share package pins with the following signals:
EPA0/P1.0/T2CLK, EPA1/P1.1, EPA2/P1.2/T2DIR, EPA3/P1.3,
EPA8/P6.0/COMP0, and EPA9/P6.1/COMP1. EPA7 does not connect to a
package pin. It cannot be used to capture an event, but it can function as a
software timer. EPA6:4 are not implemented.




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