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83C196EA Datasheet(PDF) 1 Page - Intel Corporation

Part No. 83C196EA
Description  CHMOS 16-BIT MICROCONTROLLER
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Maker  INTEL [Intel Corporation]
Homepage  http://www.intel.com
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ADVANCE INFORMATION
COPYRIGHT © INTEL CORPORATION, 1997
March 1997
Order Number: 272788-002
83C196EA
CHMOS 16-BIT MICROCONTROLLER
Automotive
The 83C196EA is the first member of a new family of microcontrollers with features that are useful in
automotive applications, such as powertrain control. Two Mbytes of linear address space provide more space
for high-level language compilation. A demultiplexed address/data bus and three chip-select signals make it
easier to design low-cost memory solutions. The external bus can dynamically switch between multiplexed
and demultiplexed operation.
NOTE
This datasheet contains information on products being sampled or in the initial production
phase of development. The specifications are subject to change without notice. Verify
with your local Intel sales office that you have the latest datasheet before finalizing a
design.
s 40 MHz operation
s Optional clock doubler
s 2 Mbytes of linear address space
s 1 Kbyte of register RAM
s 3 Kbytes of code RAM
s 8 Kbytes of ROM
s Register-to-register architecture
s Stack overflow/underflow monitor with
user-defined upper and lower stack
pointer boundary limits
s 2 peripheral interrupt handlers (PIH)
provide direct hardware handling of up
to 16 peripheral interrupts
s Peripheral transaction server (PTS) with
high-speed, microcoded interrupt
service routines
s Up to 83 I/O port pins
s 2 full-duplex serial ports with dedicated
baud-rate generators
s Enhanced synchronous serial unit
s 8 pulse-width modulator (PWM) outputs
with 8-bit resolution
s 16-bit watchdog timer
s Sixteen 10-bit A/D channels with auto-
scan mode and dedicated results
registers
s Serial debug unit provides read and
write access to code RAM with no CPU
overhead
s Chip-select unit (CSU)
s 3 chip-select pins
s Dynamic demultiplexed/multiplexed
address/data bus for each
chip-select
s Programmable wait states
(0, 1, 2, or 3) for each chip-select
s Programmable bus width
(8- or 16-bit) for each chip-select
s Programmable address range for each
chip-select
s Event processor array (EPA)
s 4 flexible 16-bit timer/counters
s 17 high-speed capture/compare
channels
s 8 output-only channels capture value of
any other timer upon compare, providing
easy conversion between angle and time
domains
s Programmable clock output signal
s 160-pin QFP package
s Complete system development support
s High-speed CHMOS technology




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