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N8259A Datasheet(PDF) 2 Page - Intel Corporation

Part # N8259A
Description  PROGRAMMABLE INTERRUPT CONTROLLER
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

N8259A Datasheet(HTML) 2 Page - Intel Corporation

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8259A
Table 1 Pin Description
Symbol
Pin No
Type
Name and Function
VCC
28
I
SUPPLY a
5V Supply
GND
14
I
GROUND
CS
1I
CHIP SELECT
A low on this pin enables RD and WR communication
between the CPU and the 8259A INTA functions are independent of
CS
WR
2I
WRITE
A low on this pin when CS is low enables the 8259A to accept
command words from the CPU
RD
3I
READ
A low on this pin when CS is low enables the 8259A to release
status onto the data bus for the CPU
D7–D0
4–11
I O
BIDIRECTIONAL DATA BUS
Control status and interrupt-vector
information is transferred via this bus
CAS0–CAS2
12 13 15
IO
CASCADE LINES
The CAS lines form a private 8259A bus to control
a multiple 8259A structure These pins are outputs for a master 8259A
and inputs for a slave 8259A
SP EN
16
IO
SLAVE PROGRAMENABLE BUFFER
This is a dual function pin
When in the Buffered Mode it can be used as an output to control
buffer transceivers (EN) When not in the buffered mode it is used as
an input to designate a master (SP e 1) or slave (SP e 0)
INT
17
O
INTERRUPT
This pin goes high whenever a valid interrupt request is
asserted It is used to interrupt the CPU thus it is connected to the
CPU’s interrupt pin
IR0–IR7
18–25
I
INTERRUPT REQUESTS
Asynchronous inputs An interrupt request
is executed by raising an IR input (low to high) and holding it high until
it is acknowledged (Edge Triggered Mode) or just by a high level on an
IR input (Level Triggered Mode)
INTA
26
I
INTERRUPT ACKNOWLEDGE
This pin is used to enable 8259A
interrupt-vector data onto the data bus by a sequence of interrupt
acknowledge pulses issued by the CPU
A0
27
I
AO ADDRESS LINE
This pin acts in conjunction with the CS WR and
RD pins It is used by the 8259A to decipher various Command Words
the CPU writes and status the CPU wishes to read It is typically
connected to the CPU A0 address line (A1 for 8086 8088)
2


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