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S80L186EC13 Datasheet(PDF) 7 Page - Intel Corporation |
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S80L186EC13 Datasheet(HTML) 7 Page - Intel Corporation |
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7 / 57 page  80C186EC188EC 80L186EC188EC Programmable Interrupt Controllers The 80C186EC utilizes two 8259A compatible Pro- grammable Interrupt Controllers (PIC) to manage both internal and external interrupts The 8259A modules are configured in a masterslave arrange- ment Seven of the external interrupt pins INT0 through INT6 are connected to the master 8259A module The eighth external interrupt pin INT7 is connected to the slave 8259A module There are a total of 11 internal interrupt sources from the integrated peripherals 4 Serial 4 DMA and 3 TimerCounter TimerCounter Unit The 80C186EC TimerCounter Unit (TCU) provides three 16-bit programmable timers Two of these are highly flexible and are connected to external pins for external control or clocking The third timer is not connected to any external pins and can only be clocked internally However it can be used to clock the other two timer channels The TCU can be used to count external events time external events gen- erate non-repetitive waveforms or generate timed in- terrupts Serial Communications Unit The 80C186EC Serial Communications Unit (SCU) contains two independent channels Each channel is identical in operation except that only channel 0 is directly supported by the integrated interrupt control- ler (the channel 1 interrupts are routed to external interrupt pins) Each channel has its own baud rate generator and can be internally or externally clocked up to one half the processor operating frequency Both serial channels can request service from the DMA unit thus providing block reception and trans- mission without CPU intervention Independent baud rate generators are provided for each of the serial channels For the asynchronous modes the generator supplies an 8x baud clock to both the receive and transmit shifting register logic A 1x baud clock is provided in the synchronous mode DMA Unit The four channel Direct Memory Access (DMA) Unit is comprised of two modules with two channels each All four channels are identical in operation DMA transfers can take place from memory to mem- ory IO to memory memory to IO or IO to IO DMA requests can be external (on the DRQ pins) internal (from Timer 2 or a serial channel) or soft- ware initiated The DMA Unit transfers data as bytes only Each data transfer requires at least two bus cycles one to fetch data and one to deposit The minimum clock count for each transfer is 8 but this will vary depend- ing on synchronization and wait states Chip-Select Unit The 80C186EC Chip-Select Unit (CSU) integrates logic which provides up to ten programmable chip- selects to access both memories and peripherals In addition each chip-select can be programmed to automatically insert additional clocks (wait states) into the current bus cycle andor automatically ter- minate a bus cycle independent of the condition of the READY input pin IO Port Unit The IO Port Unit on the 80C186EC supports two 8-bit channels and one 6-bit channel of input output or inputoutput operation Port 1 is multiplexed with the chip select pins and is output only Port 2 is mul- tiplexed with the pins for serial channels 1 and 2 All Port 2 pins are inputoutput Port 3 has a total of 6 pins four that are multiplexed with DMA and serial port interrupts and two that are non-multiplexed open drain IO Refresh Control Unit The Refresh Control Unit (RCU) automatically gen- erates a periodic memory read bus cycle to keep dynamic or pseudo-static memory refreshed A 9-bit counter controls the number of clocks between re- fresh requests A 12-bit address generator is maintained by the RCU and is presented on the A121 address lines during the refresh bus cycle Address bits A1913 are pro- grammable to allow the refresh address block to be located on any 8 Kbyte boundary Watchdog Timer Unit The Watchdog Timer Unit (WDT) allows for graceful recovery from unexpected hardware and software upsets The WDT consists of a 32-bit counter that decrements every clock cycle If the counter reach- es zero before being reset the WDTOUT pin is 7 |
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