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N80C186XL Datasheet(PDF) 5 Page - Intel Corporation |
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N80C186XL Datasheet(HTML) 5 Page - Intel Corporation |
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5 / 48 page  80C186XL80C188XL Bus Interface Unit The 80C186XL provides a local bus controller to generate the local bus control signals In addition it employs a HOLDHLDA protocol for relinquishing the local bus to other bus masters It also provides outputs that can be used to enable external buffers and to direct the flow of data on and off the local bus The bus controller is responsible for generating 20 bits of address read and write strobes bus cycle status information and data (for write operations) in- formation It is also responsible for reading data from the local bus during a read operation Synchro- nous and asynchronous ready input pins are provid- ed to extend a bus cycle beyond the minimum four states (clocks) The 80C186XL bus controller also generates two control signals (DEN and DTR) when interfacing to external transceiver chips This capability allows the addition of transceivers for simple buffering of the multiplexed addressdata bus During RESET the local bus controller will perform the following action Drive DEN RD and WR HIGH for one clock cy- cle then float them Drive S0–S2 to the inactive state (all HIGH) and then float Drive LOCK HIGH and then float Float AD0–15 (AD0–8) A16–19 (A9–A19) BHE (RFSH) DTR Drive ALE LOW Drive HLDA LOW RD QSMD UCS LCS MCS0 PEREQ MCS1 ERROR and TEST BUSY pins have internal pullup devices which are active while RES is applied Ex- cessive loading or grounding certain of these pins causes the 80C186XL to enter an alternative mode of operation RD QSMD low results in Queue Status Mode UCS and LCS low results in ONCE Mode TEST BUSY low (and high later) results in En- hanced Mode 80C186XL PERIPHERAL ARCHITECTURE All the 80C186XL integrated peripherals are con- trolled by 16-bit registers contained within an inter- nal 256-byte control block The control block may be mapped into either memory or IO space Internal logic will recognize control block addresses and re- spond to bus cycles An offset map of the 256-byte control register block is shown in Figure 3 Chip-SelectReady Generation Logic The 80C186XL contains logic which provides programmable chip-select generation for both mem- ories and peripherals In addition it can be programmed to provide READY (or WAIT state) gen- eration It can also provide latched address bits A1 and A2 The chip-select lines are active for all mem- ory and IO cycles in their programmed areas whether they be generated by the CPU or by the integrated DMA unit The 80C186XL provides 6 memory chip select out- puts for 3 address areas upper memory lower memory and midrange memory One each is provid- ed for upper memory and lower memory while four are provided for midrange memory OFFSET Relocation Register FEH DMA Descriptors Channel 1 DAH D0H DMA Descriptors Channel 0 CAH C0H Chip-Select Control Registers A8H A0H Time 2 Control Registers 66H 60H Time 1 Control Registers 5EH 58H Time 0 Control Registers 56H 50H Interrupt Controller Registers 3EH 20H Figure 3 Internal Register Map The 80C186XL provides a chip select called UCS for the top of memory The top of memory is usually used as the system memory because after reset the 80C186XL begins executing at memory location FFFF0H 5 5 |
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Similar Description - N80C186XL |
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