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82451NX Datasheet(PDF) 5 Page - Intel Corporation

Part # 82451NX
Description  Intel 450NX PCIset
Download  248 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82451NX Datasheet(HTML) 5 Page - Intel Corporation

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Intel® 450NX PCIset
-iii-
CONTENTS
3.4.8
GAPEN: Gap Enables ................................................................................................................
3-36
3.4.9
HDR: Header Type Register ......................................................................................................
3-36
3.4.10
HXGB: High Expansion Gap Base .............................................................................................
3-36
3.4.11
HXGT: High Expansion Gap Top ...............................................................................................
3-36
3.4.12
IOABASE: I/O APIC Base Address ............................................................................................
3-37
3.4.13
ISA: ISA Space ..........................................................................................................................
3-37
3.4.14
LXGB: Low Expansion Gap Base ..............................................................................................
3-37
3.4.15
LXGT: Low Expansion Gap Top ................................................................................................
3-37
3.4.16
MAR[6:0]: Memory Attribute Region Registers ..........................................................................
3-38
3.4.17
MLT: Master Latency Timer Register .........................................................................................
3-38
3.4.18
MMBASE: Memory-Mapped PCI Base .....................................................................................
3-38
3.4.19
MMT: Memory-Mapped PCI Top ...............................................................................................
3-39
3.4.20
MTT: Multi-Transaction Timer Register .....................................................................................
3-39
3.4.21
PCICMD: PCI Command Register .............................................................................................
3-39
3.4.22
PCISTS: PCI Status Register ....................................................................................................
3-40
3.4.23
PMD[1:0]: Performance Monitoring Data Register .....................................................................
3-41
3.4.24
PME[1:0]: Performance Monitoring Event Selection ..................................................................
3-42
3.4.25
PMR[1:0]: Performance Monitoring Response ..........................................................................
3-43
3.4.26
RID: Revision Identification Register .........................................................................................
3-44
3.4.27
RC: Reset Control Register .......................................................................................................
3-44
3.4.28
ROUTE: Route Field Seed .........................................................................................................
3-45
3.4.29
SMRAM: SMM RAM Control Register .......................................................................................
3-45
3.4.30
TCAP: Target Capacity ..............................................................................................................
3-46
3.4.31
TMODE: Timer Mode .................................................................................................................
3-46
3.4.32
TOM: Top of Memory .................................................................................................................
3-47
3.4.33
VID: Vendor Identification Register ............................................................................................
3-47
Chapter 4
System Address Maps ....................................................................................................................... 4-1
4.1
Memory Address Map .................................................................................................................................
4-1
4.1.1
Memory-Mapped I/O Spaces ........................................................................................................
4-4
4.1.2
SMM RAM Support .......................................................................................................................
4-4
4.2
I/O Space ....................................................................................................................................................
4-5
4.3
PCI Configuration Space .............................................................................................................................
4-6
Chapter 5
Interfaces ............................................................................................................................................. 5-1
5.1
System Bus .................................................................................................................................................
5-1
5.2
PCI Bus .......................................................................................................................................................
5-1
5.3
Expander Bus ..............................................................................................................................................
5-1
5.3.1
Expander Electrical Signal and Clock Distribution ........................................................................
5-2
5.4
Third-Party Agents ......................................................................................................................................
5-2
5.5
Connectors ..................................................................................................................................................
5-3
Chapter 6
Memory Subsystem ............................................................................................................................ 6-1
6.1
Overview .....................................................................................................................................................
6-1
6.1.1
Physical Organization ...................................................................................................................
6-1
6.1.2
Configuration Rules and Limitations .............................................................................................
6-3
6.1.2.1
Interleaving ..................................................................................................................
6-3
6.1.2.2
Address Bit Permuting Rules and Limitations .............................................................
6-4
6.1.2.3
Card to Card (C2C) Interleaving Rules and limitations ................................................
6-4
6.1.3
Address Bit Permuting ..................................................................................................................
6-5


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