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changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata

November 1995

COPYRIGHT

INTEL CORPORATION 1995

Order Number 290406-007

1-MBIT (128K x 8)

BOOT BLOCK FLASH MEMORY

28F001BX-T28F001BX-B28F001BN-T28F001BN-B

Y

High-Integration Blocked Architecture

One 8 KB Boot Block wLock Out

Two 4 KB Parameter Blocks

One 112 KB Main Block

Y

100000 EraseProgram Cycles Per

Block

Y

Simplified Program and Erase

Automated Algorithms via On-Chip

Write State Machine (WSM)

Y

SRAM-Compatible Write Interface

Y

Deep Power-Down Mode

Y

Y

High-Performance Read

7075 ns 90 ns 120 ns 150 ns

Maximum Access Time

Y

Hardware Data Protection Feature

EraseWrite Lockout during Power

Transitions

Y

Advanced Packaging JEDEC Pinouts

32-Pin PDIP

32-Lead PLCC TSOP

Y

Technology

EPROM-Compatible Process Base

High-Volume Manufacturing

Experience

Y

Extended Temperature Options

Intel’s 28F001BX-B and 28F001BX-T combine the cost-effectiveness of Intel standard flash memory with

features that simplify write and allow block erase These devices aid the system designer by combining the

functions of several components into one making boot block flash an innovative alternative to EPROM and

EEPROM or battery-backed static RAM Many new and existing designs can take advantage of the

28F001BX’s integration of blocked architecture automated electrical reprogramming and standard processor

interface

The 28F001BX-B and 28F001BX-T are 1048576 bit nonvolatile memories organized as 131072 bytes of

8 bits They are offered in 32-pin plastic DIP 32-lead PLCC and 32-lead TSOP packages Pin assignment

conform to JEDEC standards for byte-wide EPROMs These devices use an integrated command port and

state machine for simplified block erasure and byte reprogramming The 28F001BX-T’s block locations pro-

vide compatibility with microprocessors and microcontrollers that boot from high memory such as Intel’s

the 28F001BX-B memory map is tailored for microprocessors and microcontrollers that boot from low memory

such as Intel’s MCS-51 MCS-196 80960KX and 80960SX families All other features are identical and unless

otherwise noted the term 28F001BX can refer to either device throughout the remainder of this document

The boot block section includes a reprogramming write lock out feature to guarantee data integrity It is

designed to contain secure code which will bring up the system minimally and download code to the other

locations of the 28F001BX Intel’s 28F001BX employs advanced CMOS circuitry for systems requiring high-

performance access speeds low power consumption and immunity to noise Its access time provides

no-WAIT-state performance for a wide range of microprocessors and microcontrollers A deep-powerdown

mentation and other low-power applications The RP

power control input also provides absolute data protec-

tion during system powerup or power loss

Manufactured on Intel’s ETOX process base the 28F001BX builds on years of EPROM experience to yield the

highest levels of quality reliability and cost-effectiveness

NOTE

The 28F001BN is equivalent to the 28F001BX