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TB28F008SA-100 Datasheet(PDF) 10 Page - Intel Corporation |
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TB28F008SA-100 Datasheet(HTML) 10 Page - Intel Corporation |
10 / 33 page 28F008SA Data Protection Depending on the application the system designer may choose to make the VPP power supply switcha- ble (available only when memory byte writesblock erases are required) or hardwired to VPPH When VPP e VPPL memory contents cannot be altered The 28F008SA Command User Interface architec- ture provides protection from unwanted byte write or block erase operations even when high voltage is applied to VPP Additionally all functions are dis- abled whenever VCC is below the write lockout volt- age VLKO or when RP is at VIL The 28F008SA accommodates either design practice and encour- ages optimization of the processor-memory inter- face The two-step byte writeblock erase Command User Interface write sequence provides additional soft- ware write protection BUS OPERATION Flash memory reads erases and writes in-system via the local CPU All bus cycles to or from the flash memory conform to standard microprocessor bus cycles Read The 28F008SA has three read modes The memory can be read from any of its blocks and information can be read from the intelligent identifier or Status Register VPP can be at either VPPL or VPPH The first task is to write the appropriate read mode command to the Command User Interface (array in- telligent identifier or Status Register) The 28F008SA automatically resets to Read Array mode upon initial device powerup or after exit from deep powerdown The 28F008SA has four control pins two of which must be logically active to obtain data at the outputs Chip Enable (CE ) is the device se- lection control and when active enables the select- ed memory device Output Enable (OE ) is the data inputoutput (DQ0–DQ7) direction control and when active drives data from the selected memory onto the IO bus RP and WE must also be at VIH Figure 10 illustrates read bus cycle waveforms Output Disable With OE at a logic-high level (VIH) the device out- puts are disabled Output pins (DQ0–DQ7) are placed in a high-impedance state Standby CE at a logic-high level (VIH) places the 28F008SA in standby mode Standby operation disables much of the 28F008SA’s circuitry and substantially reduc- es device power consumption The outputs (DQ0– DQ7) are placed in a high-impedence state indepen- dent of the status of OE If the 28F008SA is dese- lected during block erase or byte write the device will continue functioning and consuming normal ac- tive power until the operation completes Table 2 Bus Operations Mode Notes RP CE OE WE A0 VPP DQ0–7 RYBY Read 123 VIH VIL VIL VIH XX DOUT X Output Disable 123 VIH VIL VIH VIH X X High Z X Standby 123 VIH VIH X X X X High Z X Deep PowerDown 12 VIL X X X X X High Z VOH Intelligent Identifier (Mfr) 12 VIH VIL VIL VIH VIL X 89H VOH Intelligent Identifier (Device) 12 VIH VIL VIL VIH VIH X A2H VOH Write 12345 VIH VIL VIH VIL XX DIN X NOTES 1 Refer to DC Characteristics When VPP e VPPL memory contents can be read but not written or erased 2 X can be VIL or VIH for control pins and addresses and VPPL or VPPH for VPP See DC Characteristics for VPPL and VPPH voltages 3 RYBY is VOL when the Write State Machine is executing internal block erase or byte write algorithms It is VOH when the WSM is not busy in Erase Suspend mode or deep powerdown mode 4 Command writes involving block erase or byte write are only successfully executed when VPP e VPPH 5 Refer to Table 3 for valid DIN during a write operation 10 |
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