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28F004S3 Datasheet(PDF) 7 Page - Intel Corporation |
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28F004S3 Datasheet(HTML) 7 Page - Intel Corporation |
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7 / 41 page  E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY 7 PRELIMINARY Table 1. Pin Descriptions Sym Type Name and Function A0–A20 INPUT ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. 4 Mbit → A 0–A18 8 Mbit → A 0–A19 16 Mbit → A 0–A20 DQ0–DQ7 INPUT/ OUTPUT DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs data during memory array, status register, and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. CE# INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and sense amplifiers. CE#-high deselects the device and reduces power consumption to standby levels. RP# INPUT RESET/DEEP POWER-DOWN: When driven low, RP# inhibits write operations which provides data protection during power transitions, puts the device in deep power-down mode, and resets internal automation. RP#-high enables normal operation. Exit from deep power-down sets the device to read array mode. RP# at VHH enables setting of the master lock-bit and enables configuration of block lock-bits when the master lock-bit is set. RP# = VHH overrides block lock-bits, thereby enabling block erase and program operations to locked memory blocks. Block erase, program, or lock-bit configuration with VIH < RP# < VHH produce spurious results and should not be attempted. OE# INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle. WE# INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of the WE# pulse. RY/BY# OUTPUT READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is performing an internal operation (block erase, program, or lock-bit). RY/BY#-high indicates that the WSM is ready for new commands, block erase or program is suspended, or the device is in deep power-down mode. RY/BY# is always active. VPP SUPPLY BLOCK ERASE, PROGRAM, LOCK-BIT CONFIGURATION POWER SUPPLY: For erasing array blocks, programming data, or configuring lock-bits. Smart 3 Flash → 2.7 V, 3.3 V and 12 V VPP With VPP ≤ VPPLK, memory contents cannot be altered. Block erase, program, and lock-bit configuration with an invalid VPP (see DC Characteristics) produce spurious results and should not be attempted. VCC SUPPLY DEVICE POWER SUPPLY: Internal detection automatically configures the device for optimized read performance. Do not float any power pins. Smart 3 Flash → 2.7 V and 3.3 V VCC With VCC ≤ VLKO, all write attempts to the flash memory are inhibited. Device operations at invalid VCC voltages (see DC Characteristics) produce spurious results and should not be attempted. Block erase, program, and lock-bit configuration operations with VCC < 2.7 V are not supported. GND SUPPLY GROUND: Do not float any ground pins. NC NO CONNECT: Lead is not internally connected; it may be driven or floated. |
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