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IA82510-PLC28I Datasheet(PDF) 6 Page - InnovASIC, Inc |
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IA82510-PLC28I Datasheet(HTML) 6 Page - InnovASIC, Inc |
6 / 14 page IA82510 Data Sheet ASYNCHRONOUS SERIAL CONTROLLER As of Production Ver. 01 Copyright © 2001 ENG211001219-01 www.innovasic.com innovASIC Customer Support: The End of Obsolescence ™ Page 6 of 14 1-888-824-4184 DC Characteristics Symbol Parameter Notes Min Max Unit VIL Input Low Voltage (1) -0.5 0.7 V VIH1 Input High Voltage-Cerdip (1) 2.1 VDD+.07 V VIH2 Input High Voltage-LCC (2) 2.1 VDD+.07 V VOL Output Low Voltage (2),(8) 0.4 V VOH Output High Voltage (3),(8) 2.4 V ILI Input Leakage Current (4) ±1 µA ILO 3-State Leakage Current (5) ±1 µA ICC Power Supply Current (6) 1.12 mA/MHz IPU Strapping Pullup Resistor (12) -283 -137 µA ISTBY Standby Supply Current (9) 100 µA IOHR RTSn, DTRn Strapping Current (10) 1.92 mA IOLR RTSn, DTRn Strapping Current (11) N/A mA CIN Input Capacitance (7) 5 pF CIO I/O Capacitance (7) 6 pF CXTAL X1, X2 Load 6 pF Notes: 1. Does not apply to CLK/X1 pin, when configured as crystal oscillator input (X1). 2. @IOL = 1.92 mA 3. @IOH = 1.92 mA 4. 0< VIN <VCC 5. 0.4V < VOUT < VCC – 0.4V 6. VDD = 5.5V, VIL = 0.7V (max), VIH = VDD – 0.7V (min), Typ. Val = 1.12 mA/MHz (Not Tested), Ext. 1X CLK, IOL = IOH = 0 7. Freq. = 1 MHz 8. Does not apply to OUT2/X2 pin, when configured as crystal oscillator output (X2). 9. Freq. = 1 MHz, but input clock not running. Static IDD current is exclusive of input/output drive requirements and is measured with the clocks stopped and all inputs tied to VDD or VSS, configured to draw minimum current. 10. Applies only during hardware reset for clock configuration options. Strapping current for logic HIGH. 11. Applies only during hardware reset for clock configuration options. Strapping current for logic LOW. 12. Inputs (RTSn, DTRn, TB) with Pullups tested @ Vin = 0.0V, VDD = 5.5V |
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