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IDT79R3081-33FD Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT79R3081-33FD Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 38 page 5.5 1 IDT79R3081 RISController MILITARY AND COMMERCIAL TEMPERATURE RANGES MILITARY AND COMMERCIAL TEMPERATURE RANGES SEPTEMBER 1995 ©1995 Integrated Device Technology, Inc. 5.5 DSC-9064/4 IDT 79R3081 ™, 79R3081E IDT 79RV3081, 79RV3081E IDT79R3081 RISController™ with FPA R3081 BLOCK DIAGRAM Clock Generator Unit/Clock Doubler Master Pipeline Control System Control Coprocessor (CP0) Integer CPU Core Exception/Control Registers Memory Management Registers Translation Lookaside Buffer (64 entries) General Registers (32 x 32) ALU Shifter Mult/Div Unit Address Adder PC Control Virtual Address Configurable Data Cache (4kB/8kB) Configurable Instruction Cache (16kB/8kB) Physical Address Bus BIU Control DMA Arbiter 4-deep Write Buffer ClkIn Int(5:0) 32 36 BrCond(3:2,0) Data Bus R3051 Superset Bus Interface Unit Address/ Data DMA Ctrl Rd/Wr Ctrl SysClk Register Unit (16 x 64) Exponent Unit Add Unit Divide Unit Multiply Unit Floating Point Coprocessor (CP1) Coherency Logic Invalidate Control Exception/Control Data Bus FP Interrupt Parity Generator 4-deep Read Buffer 2889 drw 01 The IDT logo is a registered trademark, and RISController, R3041, R3051, R3052, R3071, R3081, R3720, R4400, R4600, IDT/kit, and IDT/sim are trademarks of Integrated Device Technology, Inc. FEATURES • Instruction set compatible with IDT79R3000A, R3041, R3051, and R3071 RISC CPUs • High level of integration minimizes system cost — R3000A Compatible CPU — R3010A Compatible Floating Point Accelerator — Optional R3000A compatible MMU — Large Instruction Cache — Large Data Cache — Read/Write Buffers • 43VUPS at 50MHz — 13MFlops • Flexible bus interface allows simple, low cost designs • Optional 1x or 2x clock input • 20 through 50MHz operation • "V" version operates at 3.3V • 50MHz at 1x clock input and 1/2 bus frequency only • Large on-chip caches with user configurability — 16kB Instruction Cache, 4kB Data Cache — Dynamically configurable to 8kB Instruction Cache, 8kB Data Cache — Parity protection over data and tag fields • Low cost 84-pin packaging • Superset pin- and software-compatible with R3051, R3071 • Multiplexed bus interface with support for low-cost, low- speed memory systems with a high-speed CPU • On-chip 4-deep write buffer eliminates memory write stalls • On-chip 4-deep read buffer supports burst or simple block reads • On-chip DMA arbiter • Hardware-based Cache Coherency Support • Programmable power reduction mode • Bus Interface can operate at half-processor frequency Integrated Device Technology, Inc. |
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